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Apr 4th, 2020
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VHDL 0.67 KB | None | 0 0
  1. ENTITY prioridade IS
  2.   PORT (p0, p1, p2, p3 : IN BIT;
  3.           x0, x1, int    : OUT BIT);
  4. END prioridade;
  5.  
  6. ARCHITECTURE teste OF prioridade IS
  7.     SIGNAL sel: BIT_VECTOR(3 DOWNTO 0);
  8. BEGIN
  9.     sel <= p0 & p1 & p2 & p3;
  10.     abc: PROCESS (sel)
  11.     BEGIN
  12.         CASE sel IS    
  13.             WHEN "0001"             => x1 <= '1' ; x0 <= '1'; int <= '1';
  14.             WHEN "0010" | "0011"   => x1 <= '1' ; x0 <= '0'; int <= '1';
  15.             WHEN "0100" | "0101" | "0110" | "0111" => x1 <= '0' ; x0 <= '1'; int <= '1';
  16.             WHEN "1000" | "1001" | "1010" | "1011" | "1100" | "1101" | "1110" | "1111" => x1 <= '0' ; x0 <= '0'; int <= '1';
  17.             WHEN OTHERS => x1 <= '1' ; x0 <= '1'; int <= '0';
  18.         END CASE;
  19.     END PROCESS abc;
  20. END teste;
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