--------------------------------------------------------------------------------
-- SubModule DF
-- Created   12/15/2014 9:41:04 PM
--------------------------------------------------------------------------------
Library IEEE;
Use IEEE.Std_Logic_1164.all;
Use IEEE.numeric_std.all;
use work.spp_lib.all;



entity MAIN is
--generic(
  --  FACTOR  :natural := 100;
    --FBASE    :natural := 8;
    --WIDTH   :natural := 10
 -- );

 port
   (
     CLK_I    : in  STD_LOGIC;
     DATA_IN  : in  SIGNED(14 downto 0);
     DATA_OUT : out SIGNED(14 downto 0);
     ERR      : out STD_LOGIC
    );
end MAIN;


architecture Structure of MAIN is


signal DELAY, SUMOUT, SW1OUT,SW2OUT :SIGNED(14 downto 0);
signal ERR1, ERR2,ERR3,ERR4      :  STD_LOGIC;

begin

SW1 : entity WORK.z_sw
generic map(
    FACTOR  => 65,
    FBASE    => 10,
    WIDTH   => 15
    )
port map
(
     R => '0',
     C => CLK_I,
     D => DATA_IN,
     Q => SW1OUT,
     E => ERR1
);

SW2 : entity WORK.z_sw
generic map(
    FACTOR  => 170,
    FBASE    => 9,
    WIDTH   => 15
    )
port map
(
     R => '0',
     C => CLK_I,
     D => DELAY,
     Q => SW2OUT,
     E => ERR2
);

DEL : entity WORK.z_delay
generic map(
    DELAY   => 1,
    WIDTH   =>15
  )
  port map (
    R =>'0',
    C => CLK_I,
    D => DATA_IN,
    Q => DELAY
);



Sum(SW2OUT, SW1OUT,SUMOUT, ERR3);
Mult(SUMOUT,to_signed(1,16) , 1, DATA_OUT, ERR4);

ERR <= ERR1 and ERR2 and ERR3 and ERR4;





  process (CLK_I) is
  begin

     if (CLK_I'event and CLK_I='1') then
        --DELAY <=  DATA_IN;

     end if;
  end process;

end Structure;
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
-- SubModule DF
-- Created   12/15/2014 9:41:04 PM
--------------------------------------------------------------------------------
Library IEEE;
Use IEEE.Std_Logic_1164.all;
Use IEEE.numeric_std.all;

entity DF is port
   (
     DATA_IN  : in  STD_LOGIC_VECTOR(15 downto 0);
     DATA_OUT : out STD_LOGIC_VECTOR(15 downto 0);
     DIN      : in STD_LOGIC_VECTOR(7 downto 0);
     CLK_I    : in  STD_LOGIC
   );
end DF;
architecture Structure of DF is

   signal ERR :std_logic;
   signal DATEIN, DATEOUT :SIGNED(14 downto 0);

begin

  DATEIN <= SIGNED(DATA_IN(14 downto 0));
  inst :entity work.MAIN(Structure)
    port map (
     CLK_I    => DIN(0),
     DATA_IN  => DATEIN,
     DATA_OUT => DATEOUT,
     ERR      => open
    );
   DATA_OUT(14 downto 0) <= STD_LOGIC_VECTOR(DATEOUT);




end Structure;
--------------------------------------------------------------------------------