[VHDL] Modelovanje kombinacione logike odvojeno od seq

  ```
    process (clk) is
    begin
        if rising_edge(clk) then
            if rst = '1' then
                q_reg <= conv_std_logic_vector(0, WIDTH);
            else
                q_reg <= q_next;
            end if;
        end if;
    end process;

    pulse <= '1' when q_reg = conv_std_logic_vector(9, WIDTH) else
             '0';

    q_next <= conv_std_logic_vector(0, WIDTH) when q_reg < conv_std_logic_vector(9, WIDTH) else
              q_reg + 1;

  ```