sete_seg_dataflow_sem_vetor

-- PROJETO: sete_seg_dataflow_sem_vetor
-- ENTRADA A, B, C, D (tipo bit)
-- SAIDA: SA, SA, SC, SD, SD, SF, SG (tipo bit)
-- AUTORES: MARCOS MEIRA, JOAO VITOR, SALLATIEL TERFERNANDES
-- CRIACAO: 05/12/2018
-- ALTERACAO: 22/11/2019
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entity sete_seg_dataflow_sem_vetor is
    Port ( A, B, C, D : in bit;
           SA, SB, SC, SD, SE, SF, SG : out bit);
end sete_seg_dataflow_sem_vetor;

architecture decodificador of sete_seg_dataflow_sem_vetor is
begin
    SA <= not (A or C or (B xnor D));
    SB <= not ((not B) or (C xnor D));
    SC <= not (B or (not C) or D);
    SD <= not (A or ((not B) and (not D)) or ((not B) and C) or (C and (not D)) or (B and (not C) and D));
    SE <= not (((not B) and (not D)) or (C and (not D)));
    SF <= not (A or ((not C) and (not D)) or (B and (not C)) or (B and (not D)));
    SG <= not (A or (B xor C) or (C and (not D)));
end decodificador;