test bench

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY test_bench IS
END ENTITY test_bench;

ARCHITECTURE a OF test_bench IS
signal tbclk : std_logic;
signal tbrst : std_logic:= '1';
signal tbx1 : std_logic_vector(2 downto 0):="111";
signal tbx2 : std_logic_vector(2 downto 0):="111";
signal syncro : std_logic;
signal tbbtn : std_logic;
signal tby : std_logic_vector(7 downto 0);
signal syncrobtn : std_logic;
component lab92 is
Port ( clk  : in STD_LOGIC;
    srst : in STD_LOGIC;
    x1   : in STD_LOGIC_VECTOR (2 downto 0);
    x2   : in STD_LOGIC_VECTOR (2 downto 0);
    btn  : in STD_LOGIC;
    y    : out STD_LOGIC_VECTOR (7 downto 0));
end component;
BEGIN
generate_clk : process begin
    loop
        tbclk <= '0';
        wait for 25 ns;
        tbclk <= '1';
        wait for 25 ns;
        end loop;
end process;
generate_btn : process begin
    loop
        tbbtn <= '0';
        wait for 1000 ns;
        tbbtn <= '1';
        wait for 25 ns;
        end loop;
end process;
generate_rst : process begin
    tbrst <= '1', '0' after 125 ns;
    wait;
end process;
process(tbclk) begin
    if rising_edge(tbclk) then
        syncro <= tbrst;
    end if;
end process;
process(tbclk) begin
    if rising_edge(tbclk) then
        syncrobtn <= tbbtn;
    end if;
end process;
t_m : lab92
port map ( clk => tbclk,
    srst => syncro,
    x1 => tbx1,
    x2 => tbx2,
    btn => syncrobtn,
    y => tby);
END ARCHITECTURE a;