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-- Company:
-- Engineer:
--
-- Create Date: 11/05/2019 09:52:20 AM
-- Design Name:
-- Module Name: UC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity UC is
    generic (N : integer);
    Port ( clk : in STD_LOGIC;
           shrAQ : out std_logic;
           start : in STD_LOGIC;
           term : out std_logic;
           loadA : out std_logic;
           loadB : out std_logic;
           loadQ : out std_logic;
           rsta : out std_logic;
           subB : out std_logic;
           rstQM1 : out std_logic;
           q0qm1 : in std_logic_vector(1 downto 0));

end UC;

architecture Behavioral of UC is
type state_type is (sstart, sq0q1, saplus, saminusb, sshift, scscad1, sstop);
signal state : state_type ;
signal c : integer := N;
begin
    process(clk)
        begin
        if rising_edge(clk) then
            if state = sstart then
                loadB <= '1';
                rstA <= '1';
                loadQ <= '1';
                rstQM1 <= '1';
                state <= sq0q1;
            elsif state = sq0q1 then
                if q0qm1 = "01" then
                    subB <= '0';
                    state <= saplus;
                elsif q0qm1 = "10" then
                    subB <= '1';
                    state <= saminusb;
                elsif q0qm1 = "11" then
                    state <= sshift;
                elsif q0qm1 = "00" then
                    state <= sshift;
                end if;
            elsif state = saplus then
                state <= sshift;
                subB <= '0';
                loadA <= '1';
            elsif state = saminusb then
                state <= sshift;
                subB <= '1';
                loadA <= '1';
            elsif state = sshift then
                shrAQ <= '1';
            elsif state = scscad1 then
                c <= c - 1;
                if c = 0 then
                    state <= sstop;
                else
                    state <= sq0q1;
                end if;
            elsif state = sstop then
                term <= '1';
            end if;
            end if;
           end process;





end Behavioral;