TEST

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;
use STD.textio.all;
use IEEE.std_logic_textio.ALL;


entity testbench is
end entity;

architecture test of testbench is

    component dvb_s2x_interleaver
        Port(
              i_clk             :  in  std_logic;
              i_res             :  in  std_logic;
              i_enb             :  in  std_logic;
              i_modcode         :  in  std_logic_vector (7 downto 0);
              i_data            :  in  std_logic_vector (0 downto 0);
              o_data            :  out std_logic_vector (0 downto 0);
              o_data_valid      :  out std_logic
        );
     end component;

        signal      i_clk            : std_logic;
        signal      i_res            :    std_logic;
        signal      i_enb             :    std_logic;
        signal      i_modcode         :    std_logic_vector (7 downto 0);
        signal      i_data            :    std_logic_vector (0 downto 0);
        signal      o_data            :   std_logic_vector (0 downto 0);
        signal      o_data_valid      :   std_logic;

        constant clk_period : time := 1 ns;


begin

    dut: dvb_s2x_interleaver
        port map(
            i_clk => i_clk,
            i_res => i_res,
            i_enb => i_enb,
            i_modcode => i_modcode,
            i_data => i_data,
            o_data => o_data,
            o_data_valid => o_data_valid
        );

        clock: process
        begin
            wait for clk_period/2;
            i_clk <= '1';
            wait for clk_period/2;
            i_clk <= '0';
        end process;

        data: process
        begin
            i_res <= '1';
            wait for 10 ns;
            i_res <= '0';
            i_enb <= '1';
            wait for 10 ns;

            i_modcode <= "00000000";
            i_data <= "1";

        end process;
end architecture;