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  1. /*******************************************************************
  2.   Simple program to check LCD functionality on MicroZed
  3.   based MZ_APO board designed by Petr Porazil at PiKRON
  4.  
  5.   mzapo_lcdtest.c       - main and only file
  6.  
  7.   (C) Copyright 2004 - 2017 by Pavel Pisa
  8.       e-mail:   pisa@cmp.felk.cvut.cz
  9.       homepage: http://cmp.felk.cvut.cz/~pisa
  10.       work:     http://www.pikron.com/
  11.       license:  any combination GPL, LGPL, MPL or BSD licenses
  12.  
  13.  *******************************************************************/
  14.  
  15. #define _POSIX_C_SOURCE 200112L
  16.  
  17. #include <sys/mman.h>
  18. #include <stdlib.h>
  19. #include <stdio.h>
  20. #include <stdint.h>
  21. #include <unistd.h>
  22. #include <fcntl.h>
  23. #include <malloc.h>
  24. #include <string.h>
  25. #include <byteswap.h>
  26. #include <getopt.h>
  27. #include <inttypes.h>
  28. #include <time.h>
  29.  
  30. char *memdev="/dev/mem";
  31.  
  32. #define SPILED_REG_BASE_PHYS 0x43c40000
  33. #define SPILED_REG_SIZE      0x00004000
  34.  
  35. #define SPILED_REG_LED_LINE_o           0x004
  36. #define SPILED_REG_LED_RGB1_o           0x010
  37. #define SPILED_REG_LED_RGB2_o           0x014
  38. #define SPILED_REG_LED_KBDWR_DIRECT_o   0x018
  39.  
  40. #define SPILED_REG_KBDRD_KNOBS_DIRECT_o 0x020
  41. #define SPILED_REG_KNOBS_8BIT_o         0x024
  42.  
  43. #define PARLCD_REG_BASE_PHYS 0x43c00000
  44. #define PARLCD_REG_SIZE      0x00004000
  45.  
  46. #define PARLCD_REG_CMD_o                0x0008
  47. #define PARLCD_REG_DATA_o               0x000C
  48.  
  49. void *map_phys_address(off_t region_base, size_t region_size, int opt_cached)
  50. {
  51.   unsigned long mem_window_size;
  52.   unsigned long pagesize;
  53.   unsigned char *mm;
  54.   unsigned char *mem;
  55.   int fd;
  56.  
  57.   fd = open(memdev, O_RDWR | (!opt_cached? O_SYNC: 0));
  58.   if (fd < 0) {
  59.     fprintf(stderr, "cannot open %s\n", memdev);
  60.     return NULL;
  61.   }
  62.  
  63.   pagesize=sysconf(_SC_PAGESIZE);
  64.  
  65.   mem_window_size = ((region_base & (pagesize-1)) + region_size + pagesize-1) & ~(pagesize-1);
  66.  
  67.   mm = mmap(NULL, mem_window_size, PROT_WRITE|PROT_READ,
  68.               MAP_SHARED, fd, region_base & ~(pagesize-1));
  69.   mem = mm + (region_base & (pagesize-1));
  70.  
  71.   if (mm == MAP_FAILED) {
  72.     fprintf(stderr,"mmap error\n");
  73.     return NULL;
  74.   }
  75.  
  76.   return mem;
  77. }
  78.  
  79. void parlcd_write_cmd(unsigned char *parlcd_mem_base, uint16_t cmd)
  80. {
  81.   *(volatile uint16_t*)(parlcd_mem_base + PARLCD_REG_CMD_o) = cmd;
  82. }
  83.  
  84. void parlcd_write_data(unsigned char *parlcd_mem_base, uint16_t data)
  85. {
  86.   *(volatile uint16_t*)(parlcd_mem_base + PARLCD_REG_DATA_o) = data;
  87. }
  88.  
  89. void parlcd_write_data2x(unsigned char *parlcd_mem_base, uint32_t data)
  90. {
  91.   *(volatile uint32_t*)(parlcd_mem_base + PARLCD_REG_DATA_o) = data;
  92. }
  93.  
  94. void parlcd_delay(int msec)
  95. {
  96.   struct timespec wait_delay = {.tv_sec = msec / 1000,
  97.                                 .tv_nsec = (msec % 1000) * 1000 * 1000};
  98.   clock_nanosleep(CLOCK_MONOTONIC, 0, &wait_delay, NULL);
  99. }
  100.  
  101. void parlcd_hx8357_init(unsigned char *parlcd_mem_base)
  102. {
  103.   // toggle RST low to reset
  104. /*
  105.     digitalWrite(_rst, HIGH);
  106.     parlcd_delay(50);
  107.     digitalWrite(_rst, LOW);
  108.     parlcd_delay(10);
  109.     digitalWrite(_rst, HIGH);
  110.     parlcd_delay(10);
  111. */
  112.     parlcd_write_cmd(parlcd_mem_base, 0x1);
  113.     parlcd_delay(30);
  114.  
  115. #ifdef HX8357_B
  116. // Configure HX8357-B display
  117.     parlcd_write_cmd(parlcd_mem_base, 0x11);
  118.     parlcd_delay(20);
  119.     parlcd_write_cmd(parlcd_mem_base, 0xD0);
  120.     parlcd_write_data(parlcd_mem_base, 0x07);
  121.     parlcd_write_data(parlcd_mem_base, 0x42);
  122.     parlcd_write_data(parlcd_mem_base, 0x18);
  123.  
  124.     parlcd_write_cmd(parlcd_mem_base, 0xD1);
  125.     parlcd_write_data(parlcd_mem_base, 0x00);
  126.     parlcd_write_data(parlcd_mem_base, 0x07);
  127.     parlcd_write_data(parlcd_mem_base, 0x10);
  128.  
  129.     parlcd_write_cmd(parlcd_mem_base, 0xD2);
  130.     parlcd_write_data(parlcd_mem_base, 0x01);
  131.     parlcd_write_data(parlcd_mem_base, 0x02);
  132.  
  133.     parlcd_write_cmd(parlcd_mem_base, 0xC0);
  134.     parlcd_write_data(parlcd_mem_base, 0x10);
  135.     parlcd_write_data(parlcd_mem_base, 0x3B);
  136.     parlcd_write_data(parlcd_mem_base, 0x00);
  137.     parlcd_write_data(parlcd_mem_base, 0x02);
  138.     parlcd_write_data(parlcd_mem_base, 0x11);
  139.  
  140.     parlcd_write_cmd(parlcd_mem_base, 0xC5);
  141.     parlcd_write_data(parlcd_mem_base, 0x08);
  142.  
  143.     parlcd_write_cmd(parlcd_mem_base, 0xC8);
  144.     parlcd_write_data(parlcd_mem_base, 0x00);
  145.     parlcd_write_data(parlcd_mem_base, 0x32);
  146.     parlcd_write_data(parlcd_mem_base, 0x36);
  147.     parlcd_write_data(parlcd_mem_base, 0x45);
  148.     parlcd_write_data(parlcd_mem_base, 0x06);
  149.     parlcd_write_data(parlcd_mem_base, 0x16);
  150.     parlcd_write_data(parlcd_mem_base, 0x37);
  151.     parlcd_write_data(parlcd_mem_base, 0x75);
  152.     parlcd_write_data(parlcd_mem_base, 0x77);
  153.     parlcd_write_data(parlcd_mem_base, 0x54);
  154.     parlcd_write_data(parlcd_mem_base, 0x0C);
  155.     parlcd_write_data(parlcd_mem_base, 0x00);
  156.  
  157.     parlcd_write_cmd(parlcd_mem_base, 0x36);
  158.     parlcd_write_data(parlcd_mem_base, 0x0a);
  159.  
  160.     parlcd_write_cmd(parlcd_mem_base, 0x3A);
  161.     parlcd_write_data(parlcd_mem_base, 0x55);
  162.  
  163.     parlcd_write_cmd(parlcd_mem_base, 0x2A);
  164.     parlcd_write_data(parlcd_mem_base, 0x00);
  165.     parlcd_write_data(parlcd_mem_base, 0x00);
  166.     parlcd_write_data(parlcd_mem_base, 0x01);
  167.     parlcd_write_data(parlcd_mem_base, 0x3F);
  168.  
  169.     parlcd_write_cmd(parlcd_mem_base, 0x2B);
  170.     parlcd_write_data(parlcd_mem_base, 0x00);
  171.     parlcd_write_data(parlcd_mem_base, 0x00);
  172.     parlcd_write_data(parlcd_mem_base, 0x01);
  173.     parlcd_write_data(parlcd_mem_base, 0xDF);
  174.  
  175.     parlcd_delay(120);
  176.     parlcd_write_cmd(parlcd_mem_base, 0x29);
  177.  
  178.     parlcd_delay(25);
  179.  
  180. #else
  181. // HX8357-C display initialisation
  182.  
  183.     parlcd_write_cmd(parlcd_mem_base, 0xB9); // Enable extension command
  184.     parlcd_write_data(parlcd_mem_base, 0xFF);
  185.     parlcd_write_data(parlcd_mem_base, 0x83);
  186.     parlcd_write_data(parlcd_mem_base, 0x57);
  187.     parlcd_delay(50);
  188.  
  189.     parlcd_write_cmd(parlcd_mem_base, 0xB6); //Set VCOM voltage
  190.     //parlcd_write_data(parlcd_mem_base, 0x2C);    //0x52 for HSD 3.0"
  191.     parlcd_write_data(parlcd_mem_base, 0x52);    //0x52 for HSD 3.0"
  192.  
  193.     parlcd_write_cmd(parlcd_mem_base, 0x11); // Sleep off
  194.     parlcd_delay(200);
  195.  
  196.     parlcd_write_cmd(parlcd_mem_base, 0x35); // Tearing effect on
  197.     parlcd_write_data(parlcd_mem_base, 0x00);    // Added parameter
  198.  
  199.     parlcd_write_cmd(parlcd_mem_base, 0x3A); // Interface pixel format
  200.     parlcd_write_data(parlcd_mem_base, 0x55);    // 16 bits per pixel
  201.  
  202.     //parlcd_write_cmd(parlcd_mem_base, 0xCC); // Set panel characteristic
  203.     //parlcd_write_data(parlcd_mem_base, 0x09);    // S960>S1, G1>G480, R-G-B, normally black
  204.  
  205.     //parlcd_write_cmd(parlcd_mem_base, 0xB3); // RGB interface
  206.     //parlcd_write_data(parlcd_mem_base, 0x43);
  207.     //parlcd_write_data(parlcd_mem_base, 0x00);
  208.     //parlcd_write_data(parlcd_mem_base, 0x06);
  209.     //parlcd_write_data(parlcd_mem_base, 0x06);
  210.  
  211.     parlcd_write_cmd(parlcd_mem_base, 0xB1); // Power control
  212.     parlcd_write_data(parlcd_mem_base, 0x00);
  213.     parlcd_write_data(parlcd_mem_base, 0x15);
  214.     parlcd_write_data(parlcd_mem_base, 0x0D);
  215.     parlcd_write_data(parlcd_mem_base, 0x0D);
  216.     parlcd_write_data(parlcd_mem_base, 0x83);
  217.     parlcd_write_data(parlcd_mem_base, 0x48);
  218.  
  219.  
  220.     parlcd_write_cmd(parlcd_mem_base, 0xC0); // Does this do anything?
  221.     parlcd_write_data(parlcd_mem_base, 0x24);
  222.     parlcd_write_data(parlcd_mem_base, 0x24);
  223.     parlcd_write_data(parlcd_mem_base, 0x01);
  224.     parlcd_write_data(parlcd_mem_base, 0x3C);
  225.     parlcd_write_data(parlcd_mem_base, 0xC8);
  226.     parlcd_write_data(parlcd_mem_base, 0x08);
  227.  
  228.     parlcd_write_cmd(parlcd_mem_base, 0xB4); // Display cycle
  229.     parlcd_write_data(parlcd_mem_base, 0x02);
  230.     parlcd_write_data(parlcd_mem_base, 0x40);
  231.     parlcd_write_data(parlcd_mem_base, 0x00);
  232.     parlcd_write_data(parlcd_mem_base, 0x2A);
  233.     parlcd_write_data(parlcd_mem_base, 0x2A);
  234.     parlcd_write_data(parlcd_mem_base, 0x0D);
  235.     parlcd_write_data(parlcd_mem_base, 0x4F);
  236.  
  237.     parlcd_write_cmd(parlcd_mem_base, 0xE0); // Gamma curve
  238.     parlcd_write_data(parlcd_mem_base, 0x00);
  239.     parlcd_write_data(parlcd_mem_base, 0x15);
  240.     parlcd_write_data(parlcd_mem_base, 0x1D);
  241.     parlcd_write_data(parlcd_mem_base, 0x2A);
  242.     parlcd_write_data(parlcd_mem_base, 0x31);
  243.     parlcd_write_data(parlcd_mem_base, 0x42);
  244.     parlcd_write_data(parlcd_mem_base, 0x4C);
  245.     parlcd_write_data(parlcd_mem_base, 0x53);
  246.     parlcd_write_data(parlcd_mem_base, 0x45);
  247.     parlcd_write_data(parlcd_mem_base, 0x40);
  248.     parlcd_write_data(parlcd_mem_base, 0x3B);
  249.     parlcd_write_data(parlcd_mem_base, 0x32);
  250.     parlcd_write_data(parlcd_mem_base, 0x2E);
  251.     parlcd_write_data(parlcd_mem_base, 0x28);
  252.  
  253.     parlcd_write_data(parlcd_mem_base, 0x24);
  254.     parlcd_write_data(parlcd_mem_base, 0x03);
  255.     parlcd_write_data(parlcd_mem_base, 0x00);
  256.     parlcd_write_data(parlcd_mem_base, 0x15);
  257.     parlcd_write_data(parlcd_mem_base, 0x1D);
  258.     parlcd_write_data(parlcd_mem_base, 0x2A);
  259.     parlcd_write_data(parlcd_mem_base, 0x31);
  260.     parlcd_write_data(parlcd_mem_base, 0x42);
  261.     parlcd_write_data(parlcd_mem_base, 0x4C);
  262.     parlcd_write_data(parlcd_mem_base, 0x53);
  263.     parlcd_write_data(parlcd_mem_base, 0x45);
  264.     parlcd_write_data(parlcd_mem_base, 0x40);
  265.     parlcd_write_data(parlcd_mem_base, 0x3B);
  266.     parlcd_write_data(parlcd_mem_base, 0x32);
  267.  
  268.     parlcd_write_data(parlcd_mem_base, 0x2E);
  269.     parlcd_write_data(parlcd_mem_base, 0x28);
  270.     parlcd_write_data(parlcd_mem_base, 0x24);
  271.     parlcd_write_data(parlcd_mem_base, 0x03);
  272.     parlcd_write_data(parlcd_mem_base, 0x00);
  273.     parlcd_write_data(parlcd_mem_base, 0x01);
  274.  
  275.     parlcd_write_cmd(parlcd_mem_base, 0x36); // MADCTL Memory access control
  276.     //parlcd_write_data(parlcd_mem_base, 0x48);
  277.     parlcd_write_data(parlcd_mem_base, 0xE8);
  278.     parlcd_delay(20);
  279.  
  280.     parlcd_write_cmd(parlcd_mem_base, 0x21); //Display inversion on
  281.     parlcd_delay(20);
  282.  
  283.     parlcd_write_cmd(parlcd_mem_base, 0x29); // Display on
  284.  
  285.     parlcd_delay(120);
  286. #endif
  287. }
  288.  
  289. #define DISPLAY_HEIGHT 320
  290. #define DISPLAY_WIDTH 480
  291.  
  292. void drawRectangle(unsigned int *buffer1, int width, int height) {
  293.    
  294.    
  295.    
  296.     for(int i = 0; i < DISPLAY_HEIGHT; i++) {
  297.         for(int j = 0; j < DISPLAY_WIDTH; j++) {
  298.             if(i < height && j < width) buffer1[DISPLAY_WIDTH * i + j] = 0xf800;
  299.             else buffer1[DISPLAY_WIDTH * i + j] = 0xffff;
  300.         }
  301.     }
  302.    
  303.     for(int i = 0; i < DISPLAY_HEIGHT; i++) {
  304.         for(int j = 0; j < DISPLAY_WIDTH; j++) {
  305.             int x = (i - 100) * (i - 100) + (j - 100) * (j- 100);
  306.             if(x < 6000)  buffer1[DISPLAY_WIDTH * i + j] = 0x00DF;
  307.         }
  308.     }
  309.    
  310. }
  311.  
  312. int main(int argc, char *argv[])
  313. {
  314.  
  315.   unsigned char *parlcd_mem_base;
  316.   int i, j;
  317.   unsigned c;
  318.  
  319.   parlcd_mem_base = map_phys_address(PARLCD_REG_BASE_PHYS, PARLCD_REG_SIZE, 0);
  320.  
  321.   if (parlcd_mem_base == NULL)
  322.     exit(1);
  323.  
  324.   parlcd_hx8357_init(parlcd_mem_base);
  325.  
  326.   //parlcd_write_cmd(parlcd_mem_base, 0x2c);
  327.  
  328.  
  329.    
  330.     unsigned int *buffer = (unsigned int *)malloc(sizeof(unsigned int) * DISPLAY_HEIGHT * DISPLAY_WIDTH);
  331.     drawRectangle(buffer, 200, 100);
  332.  
  333.   parlcd_write_cmd(parlcd_mem_base, 0x2c);
  334.   for (i = 0; i < DISPLAY_HEIGHT ; i++) {
  335.     for (j = 0; j < DISPLAY_WIDTH ; j++) {
  336.      
  337.       parlcd_write_data(parlcd_mem_base, buffer[DISPLAY_WIDTH * i + j]);
  338.     }
  339.   }
  340.  
  341.   while (0) {
  342.      struct timespec loop_delay = {.tv_sec = 0, .tv_nsec = 200 * 1000 * 1000};
  343.  
  344.      *(volatile uint16_t*)(parlcd_mem_base + PARLCD_REG_DATA_o) = 0x0001;
  345.      *(volatile uint16_t*)(parlcd_mem_base + PARLCD_REG_DATA_o) = 0x0002;
  346.      *(volatile uint16_t*)(parlcd_mem_base + PARLCD_REG_DATA_o) = 0x0004;
  347.      *(volatile uint16_t*)(parlcd_mem_base + PARLCD_REG_DATA_o) = 0x0008;
  348.      *(volatile uint32_t*)(parlcd_mem_base + PARLCD_REG_DATA_o) = 0x0010;
  349.      *(volatile uint16_t*)(parlcd_mem_base + PARLCD_REG_DATA_o) = 0x0020;
  350.  
  351.      clock_nanosleep(CLOCK_MONOTONIC, 0, &loop_delay, NULL);
  352.   }
  353.  
  354.   return 0;
  355. }
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