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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity complemento_de_1 is
    Port ( a : in STD_LOGIC;
           m : in STD_LOGIC;
           s : out STD_LOGIC);
end complemento_de_1;

architecture Behavioral of complemento_de_1 is

begin
    s <= a xor m;
end Behavioral;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comp_de_1_de_3_bits is
    Port ( va : in STD_LOGIC_VECTOR (2 downto 0);
           md : in STD_LOGIC;
           vs : out STD_LOGIC_VECTOR (2 downto 0));
end comp_de_1_de_3_bits;

architecture Behavioral of comp_de_1_de_3_bits is
    component complemento_de_1 is
    Port ( a : in STD_LOGIC;
           m : in STD_LOGIC;
           s : out STD_LOGIC);
    end component;

begin
    r0 : complemento_de_1 port map(a => va(0), m => md, s => vs(0));
    r1 : complemento_de_1 port map(a => va(1), m => md, s => vs(1));
    r2 : complemento_de_1 port map(a => va(2), m => md, s => vs(2));
end Behavioral;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity somador_de_1_bit is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           cin : in STD_LOGIC;
           r : out STD_LOGIC;
           cout : out STD_LOGIC);
end somador_de_1_bit;

architecture Behavioral of somador_de_1_bit is

begin
    r <= a xor b xor cin;
    cout <= (a and b) or (a and cin) or (b and cin);
end Behavioral;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity somador_de_3_bits is
    Port ( va : in STD_LOGIC_VECTOR (2 downto 0);
           vb : in STD_LOGIC_VECTOR (2 downto 0);
           zin : in STD_LOGIC;
           vr : out STD_LOGIC_VECTOR (2 downto 0);
           zout : out STD_LOGIC);
end somador_de_3_bits;

architecture Behavioral of somador_de_3_bits is
    component somador_de_1_bit
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           cin : in STD_LOGIC;
           r : out STD_LOGIC;
           cout : out STD_LOGIC);
    end component;

    signal v : STD_LOGIC_VECTOR (2 downto 1);

begin
    bit1 : somador_de_1_bit port map(a => va(0), b => vb(0), cin =>  zin, r => vr(0), cout => v(1));
    bit2 : somador_de_1_bit port map(a => va(1), b => vb(1), cin => v(1), r => vr(1), cout => v(2));
    bit3 : somador_de_1_bit port map(a => va(2), b => vb(2), cin => v(2), r => vr(2), cout => zout);
end Behavioral;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity somador_subtrator is
    Port ( a_vector : in STD_LOGIC_VECTOR (2 downto 0);
           b_vector : in STD_LOGIC_VECTOR (2 downto 0);
           c_in : in STD_LOGIC;
           modo : in STD_LOGIC;
           r_vector : out STD_LOGIC_VECTOR (2 downto 0);
           c_out : out STD_LOGIC);
end somador_subtrator;

architecture Behavioral of somador_subtrator is
    component comp_de_1_de_3_bits is
    Port ( va : in STD_LOGIC_VECTOR (2 downto 0);
           md : in STD_LOGIC;
           vs : out STD_LOGIC_VECTOR (2 downto 0));
    end component;

    component somador_de_3_bits is
    Port ( va : in STD_LOGIC_VECTOR (2 downto 0);
           vb : in STD_LOGIC_VECTOR (2 downto 0);
           zin : in STD_LOGIC;
           vr : out STD_LOGIC_VECTOR (2 downto 0);
           zout : out STD_LOGIC);
    end component;

    signal s_inv : STD_LOGIC_VECTOR (2 downto 0);

begin
    P1 : comp_de_1_de_3_bits port map(va => b_vector, md => modo, vs => s_inv);
    P2 : somador_de_3_bits port map(va => a_vector, vb => s_inv, zin => modo, vr => r_vector, zout => c_out);
end Behavioral;
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