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  1.                 when propagate =>
  2.                     debug <= "000000100";
  3.                     SCK <= '1'; -- rising edge (or first bit)
  4.                     SSEL <= '0'; -- active low
  5.                     MOSI <= MOSI_PAR_reg(to_integer(count)); -- hold for two half periods
  6.  
  7.                     -- serial clock rate
  8.                     if count_clocks = serial_clock_rate then
  9.                         count_clocks <= (others => '0');
  10.                         state <= capture; -- read after write
  11.                     else
  12.                         state <= propagate; -- apparently needed to reduce logic
  13.                     end if;
  14.  
  15.                 when capture =>
  16.                     debug <= "000001000";
  17.                     SCK <= '0'; -- falling edge
  18.                     SSEL <= '0'; -- active low
  19.                     MOSI <= MOSI_PAR_reg(to_integer(count)); -- hold for two half periods
  20.                     MISO_PAR(to_integer(count)) <= MISO; -- read from slave
  21.  
  22.                     -- serial clock rate
  23.                     if count_clocks = serial_clock_rate then
  24.                         count_clocks <= (others => '0');
  25.                         count <= count - 1; -- progress the countdown
  26.                         if count = 0 then
  27.                             state <= finalize; -- that was the last bit
  28.                         else
  29.                             state <= propagate; -- more bits
  30.                         end if;
  31.                     else
  32.                         state <= capture; -- apparently needed to reduce logic
  33.                     end if;
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