library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cu is
    port (
        iCLK        :  in std_logic;
        iRST        :  in std_logic;
        iZERO       :   in std_logic;
        iSIGN       :  in std_logic;
        iCARRY  :   in std_logic;
        oREG_WE : out std_logic_vector(7 downto 0);
        oMUXA_SEL: out std_logic_vector(3 downto 0);
        oMUXB_SEL: out std_logic_vector(3 downto 0);
        oALU_SEL    : out std_logic_vector(3 downto 0)
    );
end entity;

architecture Behavioral of cu is

    type tSTATE is (IDLE, S1, S2, S3, NOP);
    signal sSTATE : tSTATE;
    signal sNEXT  : tSTATE;

    signal sREG_WE      : std_logic_vector(7 downto 0);
    signal sMUXA_SEL    : std_logic_vector(3 downto 0);
    signal sMUXB_SEL    : std_logic_vector(3 downto 0);
    signal sALU_SEL : std_logic_vector(3 downto 0);


begin

    -- Reg
    process(iCLK, iRST)begin
        if(iRST='1')then
            sSTATE <= IDLE;
        elsif(iCLK'event and iCLK='1')then

            sSTATE <= sNEXT;

        end if;
    end process;

    -- Funkcija prelaza
    process(sSTATE)begin
        case(sSTATE)is
                when IDLE   => sNEXT <= S1;
                when S1     => sNEXT <= S2;
                when S2         => sNEXT <= S3;
                when others => sNEXT <= NOP;
            end case;
    end process;

    -- Funckija izlaza
    process(sSTATE)begin
        case(sSTATE)is
            when IDLE =>
                sREG_WE         <= (others => '0');     --ovo su dozvozle za upis u registre
                sMUXA_SEL   <= (others => '0');     --nije nam vazno sta ce uci u multiplekser
                sMUXB_SEL   <= (others => '0');     --nije nam vazno al ipak iz registra R0 ce uci podatak
                sALU_SEL    <= (others => '0');

            when S1      => -- R1<=R0+1
                sREG_WE         <= "00000010";
                sMUXA_SEL   <= "0000";              --to je R0 registar
                sMUXB_SEL   <= "0000";              --ovaj deo ni ne koristimo pa nam ni ne treba moglo je i ---- sve jedno
                sALU_SEL    <= "0100";              -- A+1

            when S2      => -- R2<=R0+R1
                sREG_WE         <= "00000100";      --tu upisujemo rez to je R2
                sMUXA_SEL   <= "0000";              --selektujemo R0
                sMUXB_SEL   <= "0001";              --selektujemo R1
                sALU_SEL    <= "0001";              -- A + B

            when S3      => -- R3<=R1+R2
                sREG_WE         <= "00001000";          --selektovali izlaz u R3
                sMUXA_SEL   <= "0001";              --Sel ulaz R1
                sMUXB_SEL   <= "0010";              --sel ulaz iz R2
                sALU_SEL    <= "0001";

            when others =>
                sREG_WE         <= (others => '0');
                sMUXA_SEL   <= (others => '0');
                sMUXB_SEL   <= (others => '0');
                sALU_SEL    <= (others => '0');

        end case;

    end process;

    oREG_WE         <= sREG_WE;
    oMUXA_SEL   <= sMUXA_SEL;
    oMUXB_SEL   <= sMUXB_SEL;
    oALU_SEL        <= sALU_SEL;


end architecture;