FREQ_DIV_GEN

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-- Company:
-- Engineer:
--
-- Create Date:    11:22:54 12/15/2020
-- Design Name:
-- Module Name:    freqDivGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity freqDivGen is

generic (nfCLK:natural:=24000000);

port (cp: in STD_LOGIC;
        cp_o:buffer STD_LOGIC);

end freqDivGen;

architecture Behavioral of freqDivGen is

begin
process(cp)
variable trenutno:integer range 0 to nfCLK/2:=0;
begin
if (cp 'event and cp='1')then
trenutno:=trenutno+1;
if(trenutno>=nfCLK/2)then
cp_o<=not cp_o;
trenutno:=0;
end if;
end if;
end process;
end Behavioral;