----------------------------------------------------------------------------------
-- Company:     University of Alberta
-- Engineer:    Raza Bhatti
--
-- Create Date: 05/18/2018 09:43:23 AM
-- Design Name:
-- Module Name: SevenSegments - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SevenSegments is
    Port (
            clk:        in STD_LOGIC;
            CC :        out STD_LOGIC;      --Common cathode input to select respective 7-segment digit.
            out_7seg :  out STD_LOGIC_VECTOR (6 downto 0));
end SevenSegments;

architecture Behavioral of SevenSegments is

signal count: std_logic_vector(63 downto 0);
signal clk_out: std_logic:='0';
signal seg_select: std_logic:='0';
signal SevenSeg_Count: std_logic_vector(3 downto 0):="0000";
signal count1: std_logic_vector(63 downto 0);
signal mycc: std_logic:= '0';
begin
    CLK_OneHz: process(clk)
    begin
        if rising_edge(clk) then
            if (count1 < 1000) then
                count1 <= count1 + 1;
            else
                count1<=(others=>'0');
                mycc <= (not mycc);
                CC <= mycc;
            end if;

            if(count<125000000) then
                count<=count+'1';
            else
                count<=(others=>'0');
                clk_out<=not clk_out;
                SevenSeg_Count<=SevenSeg_Count+'1';
            end if;
        end if;
    end process;


Decoder_4to7Segment: process (clk_out)

        begin
            --Write your design lines here. Hint: use Case statement.
             case SevenSeg_Count is
                when "0000" =>
                out_7seg <= "0111111";
                when "0001" =>
                out_7seg <= "0000110";
                when "0010" =>
                out_7seg <= "1011011";
                when "0011" =>
                out_7seg <= "1001111";
                when "0100" =>
                out_7seg <= "1100110";
                when "0101" =>
                out_7seg <= "1101101";
                when "0110" =>
                out_7seg <= "1111101";
                when "0111" =>
                out_7seg <= "0000111";
                when "1000" =>
                out_7seg <= "1111111";
                when "1001" =>
                out_7seg <= "1101111";
                when "1010" =>
                out_7seg <= "1101111";
                when "1011" =>
                out_7seg <= "1111100";
                when "1100" =>
                out_7seg <= "0111001";
                when "1101" =>
                out_7seg <= "1011110";
                when "1110" =>
                out_7seg <= "1111001";
                when "1111" =>
                out_7seg <= "1110001";
             end case;

        end process;




end Behavioral;