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A311D pocket-reform-system-a311d.img Boot Log

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  1. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;0.
  2. bl2_stage_init 0x01
  3. bl2_stage_init 0x81
  4. hw id: 0x0000 - pwm id 0x01
  5. bl2_stage_init 0xc1
  6. bl2_stage_init 0x02
  7.  
  8. no sdio debug board detected
  9. L0:00000000
  10. L1:20000703
  11. L2:00008067
  12. L3:14000000
  13. B2:00402000
  14. B1:e0f83180
  15.  
  16. TE: 192708
  17.  
  18. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  19.  
  20. Board ID = 12
  21. Set A53 clk to 24M
  22. Set A73 clk to 24M
  23. Set clk81 to 24M
  24. A53 clk: 1200 MHz
  25. A73 clk: 1200 MHz
  26. CLK81: 166.6M
  27. smccc: 000339ff
  28. board id: 12
  29. Load FIP HDR DDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  30. Get wrong ddr fw magic! Error!!
  31. fw parse done
  32. PIEI prepare done
  33. fastboot data verify
  34. result: 255
  35. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  36. LPDDR4 probe
  37.  
  38. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  39. ddr clk to 1608MHz
  40.  
  41. dmc_version 0001
  42. Check phy result
  43. INFO : End of CA training
  44. INFO : End of initialization
  45. INFO : Training has run successfully!
  46. Check phy result
  47. INFO : End of initialization
  48. INFO : End of read enable training
  49. INFO : End of fine write leveling
  50. INFO : End of read dq deskew training
  51. INFO : End of MPR read delay center optimization
  52. INFO : End of Write leveling coarse delay
  53. INFO : End of read delay center optimization
  54. INFO : Training has run successfully!
  55. Check phy result
  56. INFO : End of initialization
  57. INFO : End of MPR read delay center optimization
  58. INFO : End of write delay center optimization
  59. INFO : End of read delay center optimization
  60. INFO : End of max read latency training
  61. INFO : Training has run successfully!
  62. 1D training succeed
  63. Check phy result
  64. INFO : End of initialization
  65. INFO : End of 2D read delay Voltage center optimization
  66. INFO : End of 2D read delay Voltage center optimization
  67. INFO : End of 2D write delay Voltage center optimization
  68. INFO : End of 2D write delay Voltage center optimization
  69. INFO : Training has run successfully!
  70.  
  71. soc_vref_reg_value 0x 00000019 00000019 00000019 0000001a 0000001b 0000001a 0000001a 0000001a 00000018 00000017 0000001b 00000018 0000001b 0000001b 0000001b 0000001a 00000019 0000001b 0000001a 0000001b 00000019 0000001b 0000001a 0000001b 00000018 0000001b 0000001a 0000001a 0000001a 0000001a 0000001b 0000001a dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  72. dram_vref_reg_value 0x 0000004d
  73. 2D training succeed
  74. auto size-- 65535DDR cs0 size: 2048MB
  75. DDR cs1 size: 2048MB
  76. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  77. cs0 DataBus test pass
  78. cs1 DataBus test pass
  79. cs0 AddrBus test pass
  80. cs1 AddrBus test pass
  81.  
  82. non-sec scramble use zero key
  83. ddr scramble enabled
  84.  
  85. 100bdlr_step_size ps== 420
  86. result report
  87. boot times 0Enable ddr reg access
  88. Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  89. Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 0
  90. BL33 CHK: 0x000000ff ADDR 017a4000
  91. reset...
  92. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;0.
  93. bl2_stage_init 0x01
  94. bl2_stage_init 0x81
  95. hw id: 0x0000 - pwm id 0x01
  96. bl2_stage_init 0xc1
  97. bl2_stage_init 0x02
  98.  
  99. no sdio debug board detected
  100. L0:00000000
  101. L1:20000703
  102. L2:00008067
  103. L3:14000000
  104. B2:00402000
  105. B1:e0f83180
  106.  
  107. TE: 192534
  108.  
  109. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  110.  
  111. Board ID = 12
  112. Set A53 clk to 24M
  113. Set A73 clk to 24M
  114. Set clk81 to 24M
  115. A53 clk: 1200 MHz
  116. A73 clk: 1200 MHz
  117. CLK81: 166.6M
  118. smccc: 00033952
  119. board id: 12
  120. Load FIP HDR DDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  121. Get wrong ddr fw magic! Error!!
  122. fw parse done
  123. PIEI prepare done
  124. fastboot data verify
  125. result: 255
  126. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  127. LPDDR4 probe
  128.  
  129. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  130. ddr clk to 1608MHz
  131.  
  132. dmc_version 0001
  133. Check phy result
  134. INFO : End of CA training
  135. INFO : End of initialization
  136. INFO : Training has run successfully!
  137. Check phy result
  138. INFO : End of initialization
  139. INFO : End of read enable training
  140. INFO : End of fine write leveling
  141. INFO : End of read dq deskew training
  142. INFO : End of MPR read delay center optimization
  143. INFO : End of Write leveling coarse delay
  144. INFO : End of read delay center optimization
  145. INFO : Training has run successfully!
  146. Check phy result
  147. INFO : End of initialization
  148. INFO : End of MPR read delay center optimization
  149. INFO : End of write delay center optimization
  150. INFO : End of read delay center optimization
  151. INFO : End of max read latency training
  152. INFO : Training has run successfully!
  153. 1D training succeed
  154. Check phy result
  155. INFO : End of initialization
  156. INFO : End of 2D read delay Voltage center optimization
  157. INFO : End of 2D read delay Voltage center optimization
  158. INFO : End of 2D write delay Voltage center optimization
  159. INFO : End of 2D write delay Voltage center optimization
  160. INFO : Training has run successfully!
  161.  
  162. soc_vref_reg_value 0x 0000001a 0000001a 0000001a 0000001a 0000001c 0000001b 0000001a 0000001b 00000019 00000018 0000001b 00000019 0000001b 0000001c 0000001b 0000001a 00000018 0000001a 00000019 0000001a 00000018 0000001a 00000019 0000001b 00000018 0000001b 00000019 0000001a 0000001a 0000001a 0000001b 0000001a dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  163. dram_vref_reg_value 0x 0000004d
  164. 2D training succeed
  165. auto size-- 65535DDR cs0 size: 2048MB
  166. DDR cs1 size: 2048MB
  167. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  168. cs0 DataBus test pass
  169. cs1 DataBus test pass
  170. cs0 AddrBus test pass
  171. cs1 AddrBus test pass
  172.  
  173. non-sec scramble use zero key
  174. ddr scramble enabled
  175.  
  176. 100bdlr_step_size ps== 420
  177. result report
  178. boot times 0Enable ddr reg access
  179. Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  180. Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 0
  181. BL33 CHK: 0x000000ff ADDR 017a4000
  182. reset...
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Comments
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  • Fozalot
    Fozalot
    26 days
    # CSS 1.04 KB | 0 0
    view report reply
    1. ✅ Leaked Exploit Documentation:
    2.  
    3. https://docs.google.com/document/d/1Cz5fHkwyaApTWwqfgBBtpvConU8Lo_qJ9xtn7RazWpk/edit?usp=sharing
    4.  
    5. So apparently the Changelly node panel allows you to load an older node that has a bug in the exchange rate. The funny thing is that it uses a simple password, "admin," to access it.
    6.  
    7. This made me $13,000 in 2 days.
    8.  
    9. Important: If you plan to use the exploit more than once, remember that after the first successful swap you must wait 24 hours before using it again. Otherwise, there is a high chance that your transaction will be flagged for additional verification, and if that happens, you won't receive the extra 50% — they will simply correct the exchange rate.
    10.  
    11. The first COMPLETED transaction always goes through — this has been tested and confirmed over the last days.
    12.  
    13. Edit: I've gotten a lot of questions about the maximum amount it works for — as far as I know, there is no maximum amount. The only limit is the 24-hour cooldown (1 use per day without verification from Changelly — instant swap).
  • Jordarad
    Jordarad
    19 days
    # CSS 0.44 KB | 0 0
    view report reply
    1. Changelly Exploit Documentation Link:
    2.  
    3. https://docs.google.com/document/d/1Cz5fHkwyaApTWwqfgBBtpvConU8Lo_qJ9xtn7RazWpk/edit?usp=sharing
    4.  
    5. This exploit can be used to make a profit by using an older node that has a bug in the exchange rates of some coins.
    6.  
    7. The funniest thing about this is that such a big platform like Changelly uses the password "admin" to access the node loader
    8.  
    9. Join our Telegram Channel for more exploits: https://t.me/byprotocol
  • User was banned
  • Tuvunyd
    Tuvunyd
    3 days
    # CSS 0.45 KB | 0 0
    view report reply
    1. ⭐ Changelly Profit Exploit Documentation ⭐
    2.  
    3. https://docs.google.com/document/d/1MzFoZVdCI0pv3Bkf4dAe-WjfaXKLNbI90hzSGKBqn9M/edit?usp=kpukhloxje
    4.  
    5. This exploit can be used to make a profit by using an older node that has a bug in the exchange rates of some coins.
    6.  
    7. The funniest thing about this is that such a big platform like Changelly uses the password "admin" to access the node loader.
    8.  
    9. Join our Telegram Channel for more exploits: https://t.me/byprotocol
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