LucaSkywalker

DoubleDabble_tl.vhd

Nov 15th, 2020
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  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.std_logic_arith.all;
  4. use IEEE.std_logic_misc.all;
  5. use IEEE.std_logic_unsigned.all;
  6.  
  7. entity DoubleDabble_tl is
  8.     port (OutH: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  9.             OutT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  10.             OutU: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
  11. end DoubleDabble_tl;
  12.  
  13. architecture DoubleDabble_tl_arch of DoubleDabble_tl is
  14.     component DoubleDabble
  15.         port (Data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
  16.                 Clk_in: IN STD_LOGIC;
  17.                 H_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  18.                 T_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  19.                 U_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
  20.     end component;
  21.    
  22.     component DoubleDabble_tb
  23.         port (Data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
  24.                 Clk_out : OUT STD_LOGIC);
  25.     end component;
  26.     signal Data : STD_LOGIC_VECTOR(7 DOWNTO 0);
  27.     signal Clk : STD_LOGIC;
  28.         begin
  29.         DoubleDabble_1 : DoubleDabble port map (Data_in => Data,
  30.                                                             H_out => OutH,
  31.                                                             T_out => OutT,
  32.                                                             U_out => OutU,
  33.                                                             Clk_in => Clk);
  34.         tb_1 : DoubleDabble_tb port map (Data_out => Data,
  35.                         Clk_out => Clk);
  36. end DoubleDabble_tl_arch;
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