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tb-fibonacci

DomMisterSoja Apr 9th, 2018 (edited) 22 Never
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  1. library ieee;                                                         --biblioteca utilizada: ieee
  2. use ieee.std_logic_1164.all;                                          --inclui todo o pacote padrão 1164
  3. use ieee.numeric_std.all;
  4.  
  5. entity tb_fibonacci is
  6. end entity;
  7.  
  8. architecture arch of tb_fibonacci is
  9.  
  10. component fibonacci is                                                   --inicio da declaração da entidade
  11.   port(                                                               --onde colocamos as entradas e as saidas
  12.     clk, rst : in  std_logic;                                          --entrada padrão lógico
  13.     start : in std_logic;                                             --entrada padrão lógico
  14.     i : in std_logic_vector(4 downto 0);
  15.     ready, done : out std_logic;                                      --saída padrão lógico
  16.     f : out std_logic_vector(12 downto 0)
  17. );
  18. end component;      
  19.  
  20. signal    clk, rst :  std_logic;                                          --entrada padrão lógico
  21. signal    start :  std_logic;                                             --entrada padrão lógico
  22. signal    i :  std_logic_vector(4 downto 0);
  23. signal    ready, done :  std_logic;                                      --saída padrão lógico
  24. signal    f :  std_logic_vector(12 downto 0);
  25.                                                   --
  26. begin
  27.  
  28. --device under test
  29. dut: fibonacci port map (clk, rst, start, i, ready, done, f);
  30.  
  31. process
  32. begin
  33.    clk <='0';
  34.    wait for 10ns;
  35.    clk <='1';
  36.    wait for 10ns;
  37. end process;
  38.  
  39. process
  40. begin
  41. start <='1';
  42. wait for 40ns;
  43. start <= '0';
  44. wait;
  45. end process;
  46.  
  47. process
  48. begin
  49. i <= "00100";
  50.  
  51. rst <= '1';
  52. wait for 30ns;
  53. rst <= '0';
  54. wait;
  55. end process;
  56.  
  57.  
  58. end arch;
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