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- library ieee; --biblioteca utilizada: ieee
- use ieee.std_logic_1164.all; --inclui todo o pacote padrão 1164
- use ieee.numeric_std.all;
- entity tb_fibonacci is
- end entity;
- architecture arch of tb_fibonacci is
- component fibonacci is --inicio da declaração da entidade
- port( --onde colocamos as entradas e as saidas
- clk, rst : in std_logic; --entrada padrão lógico
- start : in std_logic; --entrada padrão lógico
- i : in std_logic_vector(4 downto 0);
- ready, done : out std_logic; --saída padrão lógico
- f : out std_logic_vector(12 downto 0)
- );
- end component;
- signal clk, rst : std_logic; --entrada padrão lógico
- signal start : std_logic; --entrada padrão lógico
- signal i : std_logic_vector(4 downto 0);
- signal ready, done : std_logic; --saída padrão lógico
- signal f : std_logic_vector(12 downto 0);
- --
- begin
- --device under test
- dut: fibonacci port map (clk, rst, start, i, ready, done, f);
- process
- begin
- clk <='0';
- wait for 10ns;
- clk <='1';
- wait for 10ns;
- end process;
- process
- begin
- start <='1';
- wait for 40ns;
- start <= '0';
- wait;
- end process;
- process
- begin
- i <= "00100";
- rst <= '1';
- wait for 30ns;
- rst <= '0';
- wait;
- end process;
- end arch;
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