library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FSM_String is
    Port ( Clk : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
           LCD_Busy : in  STD_LOGIC;
           LCD_WE : out  STD_LOGIC;
           LCD_DnI : out  STD_LOGIC;
           LCD_DI : out  STD_LOGIC_VECTOR (7 downto 0));
end FSM_String;

architecture RTL of FSM_String is

  -- FSM
  type state_type is (
    sReset,
    sBusyWait,
    sWE,
    sLoop
    );

  signal State, nextState : state_type;

  -- String to print
  type LCDARRAY is array ( NATURAL range <> )
  of std_logic_vector (7 downto 0);
  type LCDBITARRAY is array ( NATURAL range <> )
  of std_logic;

  constant arrSize : positive := 9;

  constant data : LCDARRAY ( 0 to arrSize-1 ) :=
  ("00001111", X"34",  X"32" , X"33", "11000111" ,
  X"41", X"42" , X"43" , X"44");

  constant RS : LCDBITARRAY ( 0 to arrSize-1 ) :=
  (       '0',   '1',    '1',    '1',        '0',
  '1',   '1',    '1',    '1');

  signal cntIdx : natural range 0 to arrSize;

begin

  -- Character index
  process ( Clk )
  begin
    if rising_edge( Clk ) then
      if State = sReset then
        cntIdx <= 0;
      elsif State = sWE then
        cntIdx <= cntIdx + 1;
      end if;
    end if;
  end process;

  -- FSM
    process ( Clk )
  begin
    if rising_edge( Clk ) then
      if Reset = '1' then
        State <= sReset;
      else
        State <= nextState;
      end if;
    end if;
  end process;
    process( State, LCD_Busy, cntIdx )
  begin
    nextState <= State;   -- default is to stay in current State

    case State is

      when sReset =>
        nextState <= sBusyWait;

      when sBusyWait =>
        if LCD_Busy = '0' then
          nextState <= sWE;
        end if;

      when sWE =>   -- WE pulse
        nextState <= sLoop;

      when sLoop =>
        if cntIdx /= arrSize then
          nextState <= sBusyWait;
        end if;
    end case;
  end process;



 LCD_DnI <= RS(cntIdx);


 LCD_DI <= data(cntIdx);


  -- Outputs
 LCD_WE  <= '1' when State = sWE else '0';

end RTL;