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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5.  
  6. entity FSM_String is
  7.     Port ( Clk : in  STD_LOGIC;
  8.            Reset : in  STD_LOGIC;
  9.            LCD_Busy : in  STD_LOGIC;
  10.            LCD_WE : out  STD_LOGIC;
  11.            LCD_DnI : out  STD_LOGIC;
  12.            LCD_DI : out  STD_LOGIC_VECTOR (7 downto 0));
  13. end FSM_String;
  14.  
  15. architecture RTL of FSM_String is
  16.  
  17.   -- FSM
  18.   type state_type is (
  19.     sReset,
  20.     sBusyWait,
  21.     sWE,
  22.     sLoop
  23.     );
  24.    
  25.   signal State, nextState : state_type;
  26.  
  27.   -- String to print
  28.   type LCDARRAY is array ( NATURAL range <> )
  29.   of std_logic_vector (7 downto 0);
  30.   type LCDBITARRAY is array ( NATURAL range <> )
  31.   of std_logic;
  32.  
  33.   constant arrSize : positive := 9;
  34.  
  35.   constant data : LCDARRAY ( 0 to arrSize-1 ) :=
  36.   ("00001111", X"34",  X"32" , X"33", "11000111" ,
  37.   X"41", X"42" , X"43" , X"44");
  38.  
  39.   constant RS : LCDBITARRAY ( 0 to arrSize-1 ) :=
  40.   (       '0',   '1',    '1',    '1',        '0',
  41.   '1',   '1',    '1',    '1');
  42.  
  43.   signal cntIdx : natural range 0 to arrSize;
  44.  
  45. begin
  46.  
  47.   -- Character index
  48.   process ( Clk )
  49.   begin
  50.     if rising_edge( Clk ) then
  51.       if State = sReset then
  52.         cntIdx <= 0;
  53.       elsif State = sWE then
  54.         cntIdx <= cntIdx + 1;
  55.       end if;
  56.     end if;
  57.   end process;
  58.  
  59.   -- FSM
  60.     process ( Clk )
  61.   begin
  62.     if rising_edge( Clk ) then
  63.       if Reset = '1' then
  64.         State <= sReset;
  65.       else
  66.         State <= nextState;
  67.       end if;
  68.     end if;
  69.   end process;
  70.     process( State, LCD_Busy, cntIdx )
  71.   begin
  72.     nextState <= State;   -- default is to stay in current State
  73.    
  74.     case State is
  75.  
  76.       when sReset =>
  77.         nextState <= sBusyWait;
  78.  
  79.       when sBusyWait =>
  80.         if LCD_Busy = '0' then
  81.           nextState <= sWE;
  82.         end if;
  83.  
  84.       when sWE =>   -- WE pulse
  85.         nextState <= sLoop;
  86.  
  87.       when sLoop =>
  88.         if cntIdx /= arrSize then        
  89.           nextState <= sBusyWait;
  90.         end if;  
  91.     end case;
  92.   end process;
  93.  
  94.  
  95.  
  96.  LCD_DnI <= RS(cntIdx);
  97.  
  98.  
  99.  LCD_DI <= data(cntIdx);
  100.  
  101.  
  102.   -- Outputs
  103.  LCD_WE  <= '1' when State = sWE else '0';
  104.  
  105. end RTL;
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