SallatielFernandes

flipflop

Nov 26th, 2019
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VHDL 0.38 KB | None | 0 0
  1. -- Flip-flop tipo D
  2. -- Autores: João Vitor e Marcos Meira
  3. -- Data 08/02/2018
  4.  
  5. library ieee;
  6. use ieee.std_logic_1164.all;
  7.  
  8. entity flipflop is
  9. port (d, clk: in STD_LOGIC;
  10.       q: out  STD_LOGIC);
  11. end flipflop;
  12.  
  13. architecture behavioral of flipflop is  
  14. begin
  15.     process (clk)
  16.     begin
  17.         if clk'event and clk = '1' then
  18.         q <= d;
  19.         end if ;
  20.     end process;
  21. end behavioral;
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