Chingomil

Contador

Jun 28th, 2012
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VHDL 0.60 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_arith.all;
  4. use ieee.std_logic_unsigned.all;
  5. use work.std_arith.all;
  6.  
  7. entity contador is
  8. port(clk, reset, ud:in std_logic;
  9. conta: buffer std_logic_vector( 3 downto 0) );
  10.  
  11. end contador;
  12.  
  13. architecture archicontador of contador is
  14. begin
  15. process (clk)
  16. begin
  17. if (clk'event and clk='1') then
  18. if ud = '1' then  
  19. conta <= conta + 1;
  20. if (conta ="1001") then
  21. conta <= "0000";
  22. end if;
  23. end if;
  24.  
  25. if ud='0' then
  26. conta <= conta -1;
  27. if (conta = "0000") then
  28. conta <= "1001";
  29. end if;
  30. end if;
  31. end if;
  32. end process;
  33. end archicontador;
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