Nr_binar_rev

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity numarator is
    port(EN,UP,CLK,MR,LD: in std_logic;
    D:in std_logic_vector(3 downto 0);
    CR,BR:out std_logic;
    Q:out std_logic_vector(3 downto 0));
end entity;

architecture comportamentala of numarator is
begin
    process(CLK,EN,MR,LD)
    variable T:std_logic_vector(3 downto 0) := "0000";
    variable c:std_logic:='0';
    variable b:std_logic:='0';
    begin
        if(EN='0') then
            T:=T;
        else
            if(MR='1') then
                T:="0000";
            elsif(LD='1') then
                T:=D;
            elsif(CLK'event and CLK='1') then
                if(UP='0') then
                    T:=T+1;
                    if(T="1111") then c:='1';
                    else c:='0';
                    end if;
                end if;
                if(UP='1') then
                    T:=T-1;
                    if(T="0000") then b:='1';
                    else b:='0';
                    end if;
                end if;
            end if;
        end if;
        CR<=c;
        BR<=b;
        Q<=T;
    end process;
end architecture;