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  1. READ:0;0.
  2. bl2_stage_init 0x01
  3. bl2_stage_init 0x81
  4. hw id: 0x0000 - pwm id 0x01
  5. bl2_stage_init 0xc1
  6. bl2_stage_init 0x02
  7.  
  8. L0:00000000
  9. L1:20000703
  10. L2:00008067
  11. L3:14000000
  12. B2:00402000
  13. B1:e0f83180
  14.  
  15. TE: 86870
  16.  
  17. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  18.  
  19. Board ID = 12
  20. Set A53 clk to 24M
  21. Set A73 clk to 24M
  22. Set clk81 to 24M
  23. A53 clk: 1200 MHz
  24. A73 clk: 1200 MHz
  25. CLK81: 166.6M
  26. smccc: 00019c3a
  27. eMMC boot @ 1
  28. sw8 s
  29. board id: 12
  30. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  31. Get wrong ddr fw magic! Error!!
  32. fw parse done
  33. PIEI prepare done
  34. 00000000
  35. emmc switch 2 ok
  36. 00000000
  37. emmc switch 0 ok
  38. NO find ddr boot_info from eMMC
  39. fastboot data verify
  40. result: 255
  41. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  42. LPDDR4 probe
  43.  
  44. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  45. ddr clk to 1608MHz
  46. 00000000
  47. emmc switch 1 ok
  48.  
  49. dmc_version 0001
  50. Check phy result
  51. INFO : End of CA training
  52. INFO : End of initialization
  53. INFO : Training has run successfully!
  54. Check phy result
  55. INFO : End of initialization
  56. INFO : End of read enable training
  57. INFO : End of fine write leveling
  58. INFO : End of read dq deskew training
  59. INFO : End of MPR read delay center optimization
  60. INFO : End of Write leveling coarse delay
  61. INFO : End of read delay center optimization
  62. INFO : Training has run successfully!
  63. Check phy result
  64. INFO : End of initialization
  65. INFO : End of MPR read delay center optimization
  66. INFO : End of write delay center optimization
  67. INFO : End of read delay center optimization
  68. INFO : End of max read latency training
  69. INFO : Training has run successfully!
  70. 1D training succeed
  71. Check phy result
  72. INFO : End of initialization
  73. INFO : End of 2D read delay Voltage center optimization
  74. INFO : End of 2D read delay Voltage center optimization
  75. INFO : End of 2D write delay Voltage center optimization
  76. INFO : End of 2D write delay Voltage center optimization
  77. INFO : Training has run successfully!
  78.  
  79. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001c 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 0000001a 00000019 0000001c 0000001a 0000001b 0000001b 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001b 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  80. dram_vref_reg_value 0x 0000004d
  81. 2D training succeed
  82. auto size-- 65535DDR cs0 size: 2048MB
  83. DDR cs1 size: 2048MB
  84. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  85. cs0 DataBus test pass
  86. cs1 DataBus test pass
  87. cs0 AddrBus test pass
  88. cs1 AddrBus test pass
  89.  
  90. non-sec scramble use zero key
  91. ddr scramble enabled
  92.  
  93. 100bdlr_step_size ps== 420
  94. result report
  95. boot times 0Enable ddr reg access
  96. 00000000
  97. emmc switch 3 ok
  98. Authentication key not yet programmed
  99. get rpmb counter error 0x00000007
  100. 00000000
  101. emmc switch 1 ok
  102. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  103. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  104. BL33 CHK: 0x000000ff ADDR 017a4000
  105. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  106. 00000000
  107. emmc switch 2 ok
  108. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  109. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  110. 00000000
  111. emmc switch 0 ok
  112. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  113. reset...
  114. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  115. bl2_stage_init 0x01
  116. bl2_stage_init 0x81
  117. hw id: 0x0000 - pwm id 0x01
  118. bl2_stage_init 0xc1
  119. bl2_stage_init 0x02
  120.  
  121. L0:00000000
  122. L1:20000703
  123. L2:00008067
  124. L3:14000000
  125. B2:00402000
  126. B1:e0f83180
  127.  
  128. TE: 86870
  129.  
  130. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  131.  
  132. Board ID = 12
  133. Set A53 clk to 24M
  134. Set A73 clk to 24M
  135. Set clk81 to 24M
  136. A53 clk: 1200 MHz
  137. A73 clk: 1200 MHz
  138. CLK81: 166.6M
  139. smccc: 00019c3a
  140. eMMC boot @ 1
  141. sw8 s
  142. board id: 12
  143. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  144. Get wrong ddr fw magic! Error!!
  145. fw parse done
  146. PIEI prepare done
  147. 00000000
  148. emmc switch 2 ok
  149. 00000000
  150. emmc switch 0 ok
  151. NO find ddr boot_info from eMMC
  152. fastboot data verify
  153. result: 255
  154. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  155. LPDDR4 probe
  156.  
  157. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  158. ddr clk to 1608MHz
  159. 00000000
  160. emmc switch 1 ok
  161.  
  162. dmc_version 0001
  163. Check phy result
  164. INFO : End of CA training
  165. INFO : End of initialization
  166. INFO : Training has run successfully!
  167. Check phy result
  168. INFO : End of initialization
  169. INFO : End of read enable training
  170. INFO : End of fine write leveling
  171. INFO : End of read dq deskew training
  172. INFO : End of MPR read delay center optimization
  173. INFO : End of Write leveling coarse delay
  174. INFO : End of read delay center optimization
  175. INFO : Training has run successfully!
  176. Check phy result
  177. INFO : End of initialization
  178. INFO : End of MPR read delay center optimization
  179. INFO : End of write delay center optimization
  180. INFO : End of read delay center optimization
  181. INFO : End of max read latency training
  182. INFO : Training has run successfully!
  183. 1D training succeed
  184. Check phy result
  185. INFO : End of initialization
  186. INFO : End of 2D read delay Voltage center optimization
  187. INFO : End of 2D read delay Voltage center optimization
  188. INFO : End of 2D write delay Voltage center optimization
  189. INFO : End of 2D write delay Voltage center optimization
  190. INFO : Training has run successfully!
  191.  
  192. soc_vref_reg_value 0x 0000001c 0000001b 0000001c 0000001c 0000001c 0000001a 0000001d 00000017 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001c 0000001c 0000001c 0000001b 0000001c 0000001c 0000001c 0000001c 0000001b 0000001b 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  193. dram_vref_reg_value 0x 0000004d
  194. 2D training succeed
  195. auto size-- 65535DDR cs0 size: 2048MB
  196. DDR cs1 size: 2048MB
  197. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  198. cs0 DataBus test pass
  199. cs1 DataBus test pass
  200. cs0 AddrBus test pass
  201. cs1 AddrBus test pass
  202.  
  203. non-sec scramble use zero key
  204. ddr scramble enabled
  205.  
  206. 100bdlr_step_size ps== 420
  207. result report
  208. boot times 0Enable ddr reg access
  209. 00000000
  210. emmc switch 3 ok
  211. Authentication key not yet programmed
  212. get rpmb counter error 0x00000007
  213. 00000000
  214. emmc switch 1 ok
  215. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  216. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  217. BL33 CHK: 0x000000ff ADDR 017a4000
  218. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  219. 00000000
  220. emmc switch 2 ok
  221. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  222. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  223. 00000000
  224. emmc switch 0 ok
  225. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  226. reset...
  227. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  228. bl2_stage_init 0x01
  229. bl2_stage_init 0x81
  230. hw id: 0x0000 - pwm id 0x01
  231. bl2_stage_init 0xc1
  232. bl2_stage_init 0x02
  233.  
  234. L0:00000000
  235. L1:20000703
  236. L2:00008067
  237. L3:14000000
  238. B2:00402000
  239. B1:e0f83180
  240.  
  241. TE: 87009
  242.  
  243. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  244.  
  245. Board ID = 12
  246. Set A53 clk to 24M
  247. Set A73 clk to 24M
  248. Set clk81 to 24M
  249. A53 clk: 1200 MHz
  250. A73 clk: 1200 MHz
  251. CLK81: 166.6M
  252. smccc: 00019cc5
  253. eMMC boot @ 1
  254. sw8 s
  255. board id: 12
  256. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  257. Get wrong ddr fw magic! Error!!
  258. fw parse done
  259. PIEI prepare done
  260. 00000000
  261. emmc switch 2 ok
  262. 00000000
  263. emmc switch 0 ok
  264. NO find ddr boot_info from eMMC
  265. fastboot data verify
  266. result: 255
  267. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  268. LPDDR4 probe
  269.  
  270. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  271. ddr clk to 1608MHz
  272. 00000000
  273. emmc switch 1 ok
  274.  
  275. dmc_version 0001
  276. Check phy result
  277. INFO : End of CA training
  278. INFO : End of initialization
  279. INFO : Training has run successfully!
  280. Check phy result
  281. INFO : End of initialization
  282. INFO : End of read enable training
  283. INFO : End of fine write leveling
  284. INFO : End of read dq deskew training
  285. INFO : End of MPR read delay center optimization
  286. INFO : End of Write leveling coarse delay
  287. INFO : End of read delay center optimization
  288. INFO : Training has run successfully!
  289. Check phy result
  290. INFO : End of initialization
  291. INFO : End of MPR read delay center optimization
  292. INFO : End of write delay center optimization
  293. INFO : End of read delay center optimization
  294. INFO : End of max read latency training
  295. INFO : Training has run successfully!
  296. 1D training succeed
  297. Check phy result
  298. INFO : End of initialization
  299. INFO : End of 2D read delay Voltage center optimization
  300. INFO : End of 2D read delay Voltage center optimization
  301. INFO : End of 2D write delay Voltage center optimization
  302. INFO : End of 2D write delay Voltage center optimization
  303. INFO : Training has run successfully!
  304.  
  305. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001d 0000001d 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001b 0000001d 0000001b 0000001c 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c 0000001c 0000001b 0000001b 0000001d 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001d dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  306. dram_vref_reg_value 0x 0000004d
  307. 2D training succeed
  308. auto size-- 65535DDR cs0 size: 2048MB
  309. DDR cs1 size: 2048MB
  310. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  311. cs0 DataBus test pass
  312. cs1 DataBus test pass
  313. cs0 AddrBus test pass
  314. cs1 AddrBus test pass
  315.  
  316. non-sec scramble use zero key
  317. ddr scramble enabled
  318.  
  319. 100bdlr_step_size ps== 425
  320. result report
  321. boot times 0Enable ddr reg access
  322. 00000000
  323. emmc switch 3 ok
  324. Authentication key not yet programmed
  325. get rpmb counter error 0x00000007
  326. 00000000
  327. emmc switch 1 ok
  328. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  329. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  330. BL33 CHK: 0x000000ff ADDR 017a4000
  331. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  332. 00000000
  333. emmc switch 2 ok
  334. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  335. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  336. 00000000
  337. emmc switch 0 ok
  338. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  339. reset...
  340. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  341. bl2_stage_init 0x01
  342. bl2_stage_init 0x81
  343. hw id: 0x0000 - pwm id 0x01
  344. bl2_stage_init 0xc1
  345. bl2_stage_init 0x02
  346.  
  347. L0:00000000
  348. L1:20000703
  349. L2:00008067
  350. L3:14000000
  351. B2:00402000
  352. B1:e0f83180
  353.  
  354. TE: 86870
  355.  
  356. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  357.  
  358. Board ID = 12
  359. Set A53 clk to 24M
  360. Set A73 clk to 24M
  361. Set clk81 to 24M
  362. A53 clk: 1200 MHz
  363. A73 clk: 1200 MHz
  364. CLK81: 166.6M
  365. smccc: 00019c3a
  366. eMMC boot @ 1
  367. sw8 s
  368. board id: 12
  369. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  370. Get wrong ddr fw magic! Error!!
  371. fw parse done
  372. PIEI prepare done
  373. 00000000
  374. emmc switch 2 ok
  375. 00000000
  376. emmc switch 0 ok
  377. NO find ddr boot_info from eMMC
  378. fastboot data verify
  379. result: 255
  380. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  381. LPDDR4 probe
  382.  
  383. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  384. ddr clk to 1608MHz
  385. 00000000
  386. emmc switch 1 ok
  387.  
  388. dmc_version 0001
  389. Check phy result
  390. INFO : End of CA training
  391. INFO : End of initialization
  392. INFO : Training has run successfully!
  393. Check phy result
  394. INFO : End of initialization
  395. INFO : End of read enable training
  396. INFO : End of fine write leveling
  397. INFO : End of read dq deskew training
  398. INFO : End of MPR read delay center optimization
  399. INFO : End of Write leveling coarse delay
  400. INFO : End of read delay center optimization
  401. INFO : Training has run successfully!
  402. Check phy result
  403. INFO : End of initialization
  404. INFO : End of MPR read delay center optimization
  405. INFO : End of write delay center optimization
  406. INFO : End of read delay center optimization
  407. INFO : End of max read latency training
  408. INFO : Training has run successfully!
  409. 1D training succeed
  410. Check phy result
  411. INFO : End of initialization
  412. INFO : End of 2D read delay Voltage center optimization
  413. INFO : End of 2D read delay Voltage center optimization
  414. INFO : End of 2D write delay Voltage center optimization
  415. INFO : End of 2D write delay Voltage center optimization
  416. INFO : Training has run successfully!
  417.  
  418. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001c 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 0000001a 00000019 0000001c 0000001a 0000001b 0000001b 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001a 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  419. dram_vref_reg_value 0x 0000004d
  420. 2D training succeed
  421. auto size-- 65535DDR cs0 size: 2048MB
  422. DDR cs1 size: 2048MB
  423. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  424. cs0 DataBus test pass
  425. cs1 DataBus test pass
  426. cs0 AddrBus test pass
  427. cs1 AddrBus test pass
  428.  
  429. non-sec scramble use zero key
  430. ddr scramble enabled
  431.  
  432. 100bdlr_step_size ps== 431
  433. result report
  434. boot times 0Enable ddr reg access
  435. 00000000
  436. emmc switch 3 ok
  437. Authentication key not yet programmed
  438. get rpmb counter error 0x00000007
  439. 00000000
  440. emmc switch 1 ok
  441. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  442. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  443. BL33 CHK: 0x000000ff ADDR 017a4000
  444. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  445. 00000000
  446. emmc switch 2 ok
  447. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  448. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  449. 00000000
  450. emmc switch 0 ok
  451. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  452. reset...
  453. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  454. bl2_stage_init 0x01
  455. bl2_stage_init 0x81
  456. hw id: 0x0000 - pwm id 0x01
  457. bl2_stage_init 0xc1
  458. bl2_stage_init 0x02
  459.  
  460. L0:00000000
  461. L1:20000703
  462. L2:00008067
  463. L3:14000000
  464. B2:00402000
  465. B1:e0f83180
  466.  
  467. TE: 86862
  468.  
  469. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  470.  
  471. Board ID = 12
  472. Set A53 clk to 24M
  473. Set A73 clk to 24M
  474. Set clk81 to 24M
  475. A53 clk: 1200 MHz
  476. A73 clk: 1200 MHz
  477. CLK81: 166.6M
  478. smccc: 00019c32
  479. eMMC boot @ 1
  480. sw8 s
  481. board id: 12
  482. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  483. Get wrong ddr fw magic! Error!!
  484. fw parse done
  485. PIEI prepare done
  486. 00000000
  487. emmc switch 2 ok
  488. 00000000
  489. emmc switch 0 ok
  490. NO find ddr boot_info from eMMC
  491. fastboot data verify
  492. result: 255
  493. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  494. LPDDR4 probe
  495.  
  496. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  497. ddr clk to 1608MHz
  498. 00000000
  499. emmc switch 1 ok
  500.  
  501. dmc_version 0001
  502. Check phy result
  503. INFO : End of CA training
  504. INFO : End of initialization
  505. INFO : Training has run successfully!
  506. Check phy result
  507. INFO : End of initialization
  508. INFO : End of read enable training
  509. INFO : End of fine write leveling
  510. INFO : End of read dq deskew training
  511. INFO : End of MPR read delay center optimization
  512. INFO : End of Write leveling coarse delay
  513. INFO : End of read delay center optimization
  514. INFO : Training has run successfully!
  515. Check phy result
  516. INFO : End of initialization
  517. INFO : End of MPR read delay center optimization
  518. INFO : End of write delay center optimization
  519. INFO : End of read delay center optimization
  520. INFO : End of max read latency training
  521. INFO : Training has run successfully!
  522. 1D training succeed
  523. Check phy result
  524. INFO : End of initialization
  525. INFO : End of 2D read delay Voltage center optimization
  526. INFO : End of 2D read delay Voltage center optimization
  527. INFO : End of 2D write delay Voltage center optimization
  528. INFO : End of 2D write delay Voltage center optimization
  529. INFO : Training has run successfully!
  530.  
  531. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001b 0000001c 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c 0000001d 0000001c 0000001b 0000001e 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  532. dram_vref_reg_value 0x 0000004d
  533. 2D training succeed
  534. auto size-- 65535DDR cs0 size: 2048MB
  535. DDR cs1 size: 2048MB
  536. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  537. cs0 DataBus test pass
  538. cs1 DataBus test pass
  539. cs0 AddrBus test pass
  540. cs1 AddrBus test pass
  541.  
  542. non-sec scramble use zero key
  543. ddr scramble enabled
  544.  
  545. 100bdlr_step_size ps== 420
  546. result report
  547. boot times 0Enable ddr reg access
  548. 00000000
  549. emmc switch 3 ok
  550. Authentication key not yet programmed
  551. get rpmb counter error 0x00000007
  552. 00000000
  553. emmc switch 1 ok
  554. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  555. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  556. BL33 CHK: 0x000000ff ADDR 017a4000
  557. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  558. 00000000
  559. emmc switch 2 ok
  560. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  561. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  562. 00000000
  563. emmc switch 0 ok
  564. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  565. reset...
  566. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  567. bl2_stage_init 0x01
  568. bl2_stage_init 0x81
  569. hw id: 0x0000 - pwm id 0x01
  570. bl2_stage_init 0xc1
  571. bl2_stage_init 0x02
  572.  
  573. L0:00000000
  574. L1:20000703
  575. L2:00008067
  576. L3:14000000
  577. B2:00402000
  578. B1:e0f83180
  579.  
  580. TE: 87009
  581.  
  582. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  583.  
  584. Board ID = 12
  585. Set A53 clk to 24M
  586. Set A73 clk to 24M
  587. Set clk81 to 24M
  588. A53 clk: 1200 MHz
  589. A73 clk: 1200 MHz
  590. CLK81: 166.6M
  591. smccc: 00019cc5
  592. eMMC boot @ 1
  593. sw8 s
  594. board id: 12
  595. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  596. Get wrong ddr fw magic! Error!!
  597. fw parse done
  598. PIEI prepare done
  599. 00000000
  600. emmc switch 2 ok
  601. 00000000
  602. emmc switch 0 ok
  603. NO find ddr boot_info from eMMC
  604. fastboot data verify
  605. result: 255
  606. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  607. LPDDR4 probe
  608.  
  609. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  610. ddr clk to 1608MHz
  611. 00000000
  612. emmc switch 1 ok
  613.  
  614. dmc_version 0001
  615. Check phy result
  616. INFO : End of CA training
  617. INFO : End of initialization
  618. INFO : Training has run successfully!
  619. Check phy result
  620. INFO : End of initialization
  621. INFO : End of read enable training
  622. INFO : End of fine write leveling
  623. INFO : End of read dq deskew training
  624. INFO : End of MPR read delay center optimization
  625. INFO : End of Write leveling coarse delay
  626. INFO : End of read delay center optimization
  627. INFO : Training has run successfully!
  628. Check phy result
  629. INFO : End of initialization
  630. INFO : End of MPR read delay center optimization
  631. INFO : End of write delay center optimization
  632. INFO : End of read delay center optimization
  633. INFO : End of max read latency training
  634. INFO : Training has run successfully!
  635. 1D training succeed
  636. Check phy result
  637. INFO : End of initialization
  638. INFO : End of 2D read delay Voltage center optimization
  639. INFO : End of 2D read delay Voltage center optimization
  640. INFO : End of 2D write delay Voltage center optimization
  641. INFO : End of 2D write delay Voltage center optimization
  642. INFO : Training has run successfully!
  643.  
  644. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001a 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c 0000001c 0000001c 0000001b 0000001d 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  645. dram_vref_reg_value 0x 0000004d
  646. 2D training succeed
  647. auto size-- 65535DDR cs0 size: 2048MB
  648. DDR cs1 size: 2048MB
  649. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  650. cs0 DataBus test pass
  651. cs1 DataBus test pass
  652. cs0 AddrBus test pass
  653. cs1 AddrBus test pass
  654.  
  655. non-sec scramble use zero key
  656. ddr scramble enabled
  657.  
  658. 100bdlr_step_size ps== 420
  659. result report
  660. boot times 0Enable ddr reg access
  661. 00000000
  662. emmc switch 3 ok
  663. Authentication key not yet programmed
  664. get rpmb counter error 0x00000007
  665. 00000000
  666. emmc switch 1 ok
  667. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  668. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  669. BL33 CHK: 0x000000ff ADDR 017a4000
  670. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  671. 00000000
  672. emmc switch 2 ok
  673. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  674. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  675. 00000000
  676. emmc switch 0 ok
  677. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  678. reset...
  679. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  680. bl2_stage_init 0x01
  681. bl2_stage_init 0x81
  682. hw id: 0x0000 - pwm id 0x01
  683. bl2_stage_init 0xc1
  684. bl2_stage_init 0x02
  685.  
  686. L0:00000000
  687. L1:20000703
  688. L2:00008067
  689. L3:14000000
  690. B2:00402000
  691. B1:e0f83180
  692.  
  693. TE: 86870
  694.  
  695. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  696.  
  697. Board ID = 12
  698. Set A53 clk to 24M
  699. Set A73 clk to 24M
  700. Set clk81 to 24M
  701. A53 clk: 1200 MHz
  702. A73 clk: 1200 MHz
  703. CLK81: 166.6M
  704. smccc: 00019c3a
  705. eMMC boot @ 1
  706. sw8 s
  707. board id: 12
  708. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  709. Get wrong ddr fw magic! Error!!
  710. fw parse done
  711. PIEI prepare done
  712. 00000000
  713. emmc switch 2 ok
  714. 00000000
  715. emmc switch 0 ok
  716. NO find ddr boot_info from eMMC
  717. fastboot data verify
  718. result: 255
  719. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  720. LPDDR4 probe
  721.  
  722. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  723. ddr clk to 1608MHz
  724. 00000000
  725. emmc switch 1 ok
  726.  
  727. dmc_version 0001
  728. Check phy result
  729. INFO : End of CA training
  730. INFO : End of initialization
  731. INFO : Training has run successfully!
  732. Check phy result
  733. INFO : End of initialization
  734. INFO : End of read enable training
  735. INFO : End of fine write leveling
  736. INFO : End of read dq deskew training
  737. INFO : End of MPR read delay center optimization
  738. INFO : End of Write leveling coarse delay
  739. INFO : End of read delay center optimization
  740. INFO : Training has run successfully!
  741. Check phy result
  742. INFO : End of initialization
  743. INFO : End of MPR read delay center optimization
  744. INFO : End of write delay center optimization
  745. INFO : End of read delay center optimization
  746. INFO : End of max read latency training
  747. INFO : Training has run successfully!
  748. 1D training succeed
  749. Check phy result
  750. INFO : End of initialization
  751. INFO : End of 2D read delay Voltage center optimization
  752. INFO : End of 2D read delay Voltage center optimization
  753. INFO : End of 2D write delay Voltage center optimization
  754. INFO : End of 2D write delay Voltage center optimization
  755. INFO : Training has run successfully!
  756.  
  757. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001c 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 0000001a 00000019 0000001c 0000001a 0000001b 0000001b 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001a 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  758. dram_vref_reg_value 0x 0000004d
  759. 2D training succeed
  760. auto size-- 65535DDR cs0 size: 2048MB
  761. DDR cs1 size: 2048MB
  762. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  763. cs0 DataBus test pass
  764. cs1 DataBus test pass
  765. cs0 AddrBus test pass
  766. cs1 AddrBus test pass
  767.  
  768. non-sec scramble use zero key
  769. ddr scramble enabled
  770.  
  771. 100bdlr_step_size ps== 420
  772. result report
  773. boot times 0Enable ddr reg access
  774. 00000000
  775. emmc switch 3 ok
  776. Authentication key not yet programmed
  777. get rpmb counter error 0x00000007
  778. 00000000
  779. emmc switch 1 ok
  780. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  781. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  782. BL33 CHK: 0x000000ff ADDR 017a4000
  783. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  784. 00000000
  785. emmc switch 2 ok
  786. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  787. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  788. 00000000
  789. emmc switch 0 ok
  790. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  791. reset...
  792. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  793. bl2_stage_init 0x01
  794. bl2_stage_init 0x81
  795. hw id: 0x0000 - pwm id 0x01
  796. bl2_stage_init 0xc1
  797. bl2_stage_init 0x02
  798.  
  799. L0:00000000
  800. L1:20000703
  801. L2:00008067
  802. L3:14000000
  803. B2:00402000
  804. B1:e0f83180
  805.  
  806. TE: 86862
  807.  
  808. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  809.  
  810. Board ID = 12
  811. Set A53 clk to 24M
  812. Set A73 clk to 24M
  813. Set clk81 to 24M
  814. A53 clk: 1200 MHz
  815. A73 clk: 1200 MHz
  816. CLK81: 166.6M
  817. smccc: 00019c32
  818. eMMC boot @ 1
  819. sw8 s
  820. board id: 12
  821. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  822. Get wrong ddr fw magic! Error!!
  823. fw parse done
  824. PIEI prepare done
  825. 00000000
  826. emmc switch 2 ok
  827. 00000000
  828. emmc switch 0 ok
  829. NO find ddr boot_info from eMMC
  830. fastboot data verify
  831. result: 255
  832. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  833. LPDDR4 probe
  834.  
  835. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  836. ddr clk to 1608MHz
  837. 00000000
  838. emmc switch 1 ok
  839.  
  840. dmc_version 0001
  841. Check phy result
  842. INFO : End of CA training
  843. INFO : End of initialization
  844. INFO : Training has run successfully!
  845. Check phy result
  846. INFO : End of initialization
  847. INFO : End of read enable training
  848. INFO : End of fine write leveling
  849. INFO : End of read dq deskew training
  850. INFO : End of MPR read delay center optimization
  851. INFO : End of Write leveling coarse delay
  852. INFO : End of read delay center optimization
  853. INFO : Training has run successfully!
  854. Check phy result
  855. INFO : End of initialization
  856. INFO : End of MPR read delay center optimization
  857. INFO : End of write delay center optimization
  858. INFO : End of read delay center optimization
  859. INFO : End of max read latency training
  860. INFO : Training has run successfully!
  861. 1D training succeed
  862. Check phy result
  863. INFO : End of initialization
  864. INFO : End of 2D read delay Voltage center optimization
  865. INFO : End of 2D read delay Voltage center optimization
  866. INFO : End of 2D write delay Voltage center optimization
  867. INFO : End of 2D write delay Voltage center optimization
  868. INFO : Training has run successfully!
  869.  
  870. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001c 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 0000001a 00000019 0000001c 0000001a 0000001b 0000001b 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001b 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  871. dram_vref_reg_value 0x 0000004d
  872. 2D training succeed
  873. auto size-- 65535DDR cs0 size: 2048MB
  874. DDR cs1 size: 2048MB
  875. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  876. cs0 DataBus test pass
  877. cs1 DataBus test pass
  878. cs0 AddrBus test pass
  879. cs1 AddrBus test pass
  880.  
  881. non-sec scramble use zero key
  882. ddr scramble enabled
  883.  
  884. 100bdlr_step_size ps== 425
  885. result report
  886. boot times 0Enable ddr reg access
  887. 00000000
  888. emmc switch 3 ok
  889. Authentication key not yet programmed
  890. get rpmb counter error 0x00000007
  891. 00000000
  892. emmc switch 1 ok
  893. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  894. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  895. BL33 CHK: 0x000000ff ADDR 017a4000
  896. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  897. 00000000
  898. emmc switch 2 ok
  899. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  900. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  901. 00000000
  902. emmc switch 0 ok
  903. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  904. reset...
  905. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  906. bl2_stage_init 0x01
  907. bl2_stage_init 0x81
  908. hw id: 0x0000 - pwm id 0x01
  909. bl2_stage_init 0xc1
  910. bl2_stage_init 0x02
  911.  
  912. L0:00000000
  913. L1:20000703
  914. L2:00008067
  915. L3:14000000
  916. B2:00402000
  917. B1:e0f83180
  918.  
  919. TE: 86870
  920.  
  921. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  922.  
  923. Board ID = 12
  924. Set A53 clk to 24M
  925. Set A73 clk to 24M
  926. Set clk81 to 24M
  927. A53 clk: 1200 MHz
  928. A73 clk: 1200 MHz
  929. CLK81: 166.6M
  930. smccc: 00019c3a
  931. eMMC boot @ 1
  932. sw8 s
  933. board id: 12
  934. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  935. Get wrong ddr fw magic! Error!!
  936. fw parse done
  937. PIEI prepare done
  938. 00000000
  939. emmc switch 2 ok
  940. 00000000
  941. emmc switch 0 ok
  942. NO find ddr boot_info from eMMC
  943. fastboot data verify
  944. result: 255
  945. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  946. LPDDR4 probe
  947.  
  948. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  949. ddr clk to 1608MHz
  950. 00000000
  951. emmc switch 1 ok
  952.  
  953. dmc_version 0001
  954. Check phy result
  955. INFO : End of CA training
  956. INFO : End of initialization
  957. INFO : Training has run successfully!
  958. Check phy result
  959. INFO : End of initialization
  960. INFO : End of read enable training
  961. INFO : End of fine write leveling
  962. INFO : End of read dq deskew training
  963. INFO : End of MPR read delay center optimization
  964. INFO : End of Write leveling coarse delay
  965. INFO : End of read delay center optimization
  966. INFO : Training has run successfully!
  967. Check phy result
  968. INFO : End of initialization
  969. INFO : End of MPR read delay center optimization
  970. INFO : End of write delay center optimization
  971. INFO : End of read delay center optimization
  972. INFO : End of max read latency training
  973. INFO : Training has run successfully!
  974. 1D training succeed
  975. Check phy result
  976. INFO : End of initialization
  977. INFO : End of 2D read delay Voltage center optimization
  978. INFO : End of 2D read delay Voltage center optimization
  979. INFO : End of 2D write delay Voltage center optimization
  980. INFO : End of 2D write delay Voltage center optimization
  981. INFO : Training has run successfully!
  982.  
  983. soc_vref_reg_value 0x 0000001c 0000001b 0000001c 0000001d 0000001c 0000001a 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c 0000001c 0000001b 0000001b 0000001d 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001d dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  984. dram_vref_reg_value 0x 0000004d
  985. 2D training succeed
  986. auto size-- 65535DDR cs0 size: 2048MB
  987. DDR cs1 size: 2048MB
  988. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  989. cs0 DataBus test pass
  990. cs1 DataBus test pass
  991. cs0 AddrBus test pass
  992. cs1 AddrBus test pass
  993.  
  994. non-sec scramble use zero key
  995. ddr scramble enabled
  996.  
  997. 100bdlr_step_size ps== 431
  998. result report
  999. boot times 0Enable ddr reg access
  1000. 00000000
  1001. emmc switch 3 ok
  1002. Authentication key not yet programmed
  1003. get rpmb counter error 0x00000007
  1004. 00000000
  1005. emmc switch 1 ok
  1006. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  1007. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  1008. BL33 CHK: 0x000000ff ADDR 017a4000
  1009. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  1010. 00000000
  1011. emmc switch 2 ok
  1012. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1013. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  1014. 00000000
  1015. emmc switch 0 ok
  1016. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1017. reset...
  1018. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  1019. bl2_stage_init 0x01
  1020. bl2_stage_init 0x81
  1021. hw id: 0x0000 - pwm id 0x01
  1022. bl2_stage_init 0xc1
  1023. bl2_stage_init 0x02
  1024.  
  1025. L0:00000000
  1026. L1:20000703
  1027. L2:00008067
  1028. L3:14000000
  1029. B2:00402000
  1030. B1:e0f83180
  1031.  
  1032. TE: 86870
  1033.  
  1034. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  1035.  
  1036. Board ID = 12
  1037. Set A53 clk to 24M
  1038. Set A73 clk to 24M
  1039. Set clk81 to 24M
  1040. A53 clk: 1200 MHz
  1041. A73 clk: 1200 MHz
  1042. CLK81: 166.6M
  1043. smccc: 00019c3a
  1044. eMMC boot @ 1
  1045. sw8 s
  1046. board id: 12
  1047. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  1048. Get wrong ddr fw magic! Error!!
  1049. fw parse done
  1050. PIEI prepare done
  1051. 00000000
  1052. emmc switch 2 ok
  1053. 00000000
  1054. emmc switch 0 ok
  1055. NO find ddr boot_info from eMMC
  1056. fastboot data verify
  1057. result: 255
  1058. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  1059. LPDDR4 probe
  1060.  
  1061. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  1062. ddr clk to 1608MHz
  1063. 00000000
  1064. emmc switch 1 ok
  1065.  
  1066. dmc_version 0001
  1067. Check phy result
  1068. INFO : End of CA training
  1069. INFO : End of initialization
  1070. INFO : Training has run successfully!
  1071. Check phy result
  1072. INFO : End of initialization
  1073. INFO : End of read enable training
  1074. INFO : End of fine write leveling
  1075. INFO : End of read dq deskew training
  1076. INFO : End of MPR read delay center optimization
  1077. INFO : End of Write leveling coarse delay
  1078. INFO : End of read delay center optimization
  1079. INFO : Training has run successfully!
  1080. Check phy result
  1081. INFO : End of initialization
  1082. INFO : End of MPR read delay center optimization
  1083. INFO : End of write delay center optimization
  1084. INFO : End of read delay center optimization
  1085. INFO : End of max read latency training
  1086. INFO : Training has run successfully!
  1087. 1D training succeed
  1088. Check phy result
  1089. INFO : End of initialization
  1090. INFO : End of 2D read delay Voltage center optimization
  1091. INFO : End of 2D read delay Voltage center optimization
  1092. INFO : End of 2D write delay Voltage center optimization
  1093. INFO : End of 2D write delay Voltage center optimization
  1094. INFO : Training has run successfully!
  1095.  
  1096. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001d 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001c 0000001c 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001c 0000001b 0000001d 0000001b 0000001b 0000001c 0000001b 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  1097. dram_vref_reg_value 0x 0000004d
  1098. 2D training succeed
  1099. auto size-- 65535DDR cs0 size: 2048MB
  1100. DDR cs1 size: 2048MB
  1101. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  1102. cs0 DataBus test pass
  1103. cs1 DataBus test pass
  1104. cs0 AddrBus test pass
  1105. cs1 AddrBus test pass
  1106.  
  1107. non-sec scramble use zero key
  1108. ddr scramble enabled
  1109.  
  1110. 100bdlr_step_size ps== 420
  1111. result report
  1112. boot times 0Enable ddr reg access
  1113. 00000000
  1114. emmc switch 3 ok
  1115. Authentication key not yet programmed
  1116. get rpmb counter error 0x00000007
  1117. 00000000
  1118. emmc switch 1 ok
  1119. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  1120. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  1121. BL33 CHK: 0x000000ff ADDR 017a4000
  1122. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  1123. 00000000
  1124. emmc switch 2 ok
  1125. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1126. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  1127. 00000000
  1128. emmc switch 0 ok
  1129. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1130. reset...
  1131. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  1132. bl2_stage_init 0x01
  1133. bl2_stage_init 0x81
  1134. hw id: 0x0000 - pwm id 0x01
  1135. bl2_stage_init 0xc1
  1136. bl2_stage_init 0x02
  1137.  
  1138. L0:00000000
  1139. L1:20000703
  1140. L2:00008067
  1141. L3:14000000
  1142. B2:00402000
  1143. B1:e0f83180
  1144.  
  1145. TE: 86870
  1146.  
  1147. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  1148.  
  1149. Board ID = 12
  1150. Set A53 clk to 24M
  1151. Set A73 clk to 24M
  1152. Set clk81 to 24M
  1153. A53 clk: 1200 MHz
  1154. A73 clk: 1200 MHz
  1155. CLK81: 166.6M
  1156. smccc: 00019c3a
  1157. eMMC boot @ 1
  1158. sw8 s
  1159. board id: 12
  1160. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  1161. Get wrong ddr fw magic! Error!!
  1162. fw parse done
  1163. PIEI prepare done
  1164. 00000000
  1165. emmc switch 2 ok
  1166. 00000000
  1167. emmc switch 0 ok
  1168. NO find ddr boot_info from eMMC
  1169. fastboot data verify
  1170. result: 255
  1171. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  1172. LPDDR4 probe
  1173.  
  1174. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  1175. ddr clk to 1608MHz
  1176. 00000000
  1177. emmc switch 1 ok
  1178.  
  1179. dmc_version 0001
  1180. Check phy result
  1181. INFO : End of CA training
  1182. INFO : End of initialization
  1183. INFO : Training has run successfully!
  1184. Check phy result
  1185. INFO : End of initialization
  1186. INFO : End of read enable training
  1187. INFO : End of fine write leveling
  1188. INFO : End of read dq deskew training
  1189. INFO : End of MPR read delay center optimization
  1190. INFO : End of Write leveling coarse delay
  1191. INFO : End of read delay center optimization
  1192. INFO : Training has run successfully!
  1193. Check phy result
  1194. INFO : End of initialization
  1195. INFO : End of MPR read delay center optimization
  1196. INFO : End of write delay center optimization
  1197. INFO : End of read delay center optimization
  1198. INFO : End of max read latency training
  1199. INFO : Training has run successfully!
  1200. 1D training succeed
  1201. Check phy result
  1202. INFO : End of initialization
  1203. INFO : End of 2D read delay Voltage center optimization
  1204. INFO : End of 2D read delay Voltage center optimization
  1205. INFO : End of 2D write delay Voltage center optimization
  1206. INFO : End of 2D write delay Voltage center optimization
  1207. INFO : Training has run successfully!
  1208.  
  1209. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001d 0000001c 0000001a 0000001d 00000017 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001b 00000019 0000001b 0000001b 0000001b 0000001b 0000001a 0000001a 0000001c 0000001a 0000001b 0000001b 0000001a 0000001b 0000001c 0000001b dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  1210. dram_vref_reg_value 0x 0000004e
  1211. 2D training succeed
  1212. auto size-- 65535DDR cs0 size: 2048MB
  1213. DDR cs1 size: 2048MB
  1214. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  1215. cs0 DataBus test pass
  1216. cs1 DataBus test pass
  1217. cs0 AddrBus test pass
  1218. cs1 AddrBus test pass
  1219.  
  1220. non-sec scramble use zero key
  1221. ddr scramble enabled
  1222.  
  1223. 100bdlr_step_size ps== 425
  1224. result report
  1225. boot times 0Enable ddr reg access
  1226. 00000000
  1227. emmc switch 3 ok
  1228. Authentication key not yet programmed
  1229. get rpmb counter error 0x00000007
  1230. 00000000
  1231. emmc switch 1 ok
  1232. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  1233. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  1234. BL33 CHK: 0x000000ff ADDR 017a4000
  1235. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  1236. 00000000
  1237. emmc switch 2 ok
  1238. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1239. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  1240. 00000000
  1241. emmc switch 0 ok
  1242. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1243. reset...
  1244. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  1245. bl2_stage_init 0x01
  1246. bl2_stage_init 0x81
  1247. hw id: 0x0000 - pwm id 0x01
  1248. bl2_stage_init 0xc1
  1249. bl2_stage_init 0x02
  1250.  
  1251. L0:00000000
  1252. L1:20000703
  1253. L2:00008067
  1254. L3:14000000
  1255. B2:00402000
  1256. B1:e0f83180
  1257.  
  1258. TE: 86992
  1259.  
  1260. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  1261.  
  1262. Board ID = 12
  1263. Set A53 clk to 24M
  1264. Set A73 clk to 24M
  1265. Set clk81 to 24M
  1266. A53 clk: 1200 MHz
  1267. A73 clk: 1200 MHz
  1268. CLK81: 166.6M
  1269. smccc: 00019cb4
  1270. eMMC boot @ 1
  1271. sw8 s
  1272. board id: 12
  1273. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  1274. Get wrong ddr fw magic! Error!!
  1275. fw parse done
  1276. PIEI prepare done
  1277. 00000000
  1278. emmc switch 2 ok
  1279. 00000000
  1280. emmc switch 0 ok
  1281. NO find ddr boot_info from eMMC
  1282. fastboot data verify
  1283. result: 255
  1284. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  1285. LPDDR4 probe
  1286.  
  1287. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  1288. ddr clk to 1608MHz
  1289. 00000000
  1290. emmc switch 1 ok
  1291.  
  1292. dmc_version 0001
  1293. Check phy result
  1294. INFO : End of CA training
  1295. INFO : End of initialization
  1296. INFO : Training has run successfully!
  1297. Check phy result
  1298. INFO : End of initialization
  1299. INFO : End of read enable training
  1300. INFO : End of fine write leveling
  1301. INFO : End of read dq deskew training
  1302. INFO : End of MPR read delay center optimization
  1303. INFO : End of Write leveling coarse delay
  1304. INFO : End of read delay center optimization
  1305. INFO : Training has run successfully!
  1306. Check phy result
  1307. INFO : End of initialization
  1308. INFO : End of MPR read delay center optimization
  1309. INFO : End of write delay center optimization
  1310. INFO : End of read delay center optimization
  1311. INFO : End of max read latency training
  1312. INFO : Training has run successfully!
  1313. 1D training succeed
  1314. Check phy result
  1315. INFO : End of initialization
  1316. INFO : End of 2D read delay Voltage center optimization
  1317. INFO : End of 2D read delay Voltage center optimization
  1318. INFO : End of 2D write delay Voltage center optimization
  1319. INFO : End of 2D write delay Voltage center optimization
  1320. INFO : Training has run successfully!
  1321.  
  1322. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001c 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 00000019 00000019 0000001c 0000001a 0000001b 0000001b 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001a 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  1323. dram_vref_reg_value 0x 0000004d
  1324. 2D training succeed
  1325. auto size-- 65535DDR cs0 size: 2048MB
  1326. DDR cs1 size: 2048MB
  1327. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  1328. cs0 DataBus test pass
  1329. cs1 DataBus test pass
  1330. cs0 AddrBus test pass
  1331. cs1 AddrBus test pass
  1332.  
  1333. non-sec scramble use zero key
  1334. ddr scramble enabled
  1335.  
  1336. 100bdlr_step_size ps== 420
  1337. result report
  1338. boot times 0Enable ddr reg access
  1339. 00000000
  1340. emmc switch 3 ok
  1341. Authentication key not yet programmed
  1342. get rpmb counter error 0x00000007
  1343. 00000000
  1344. emmc switch 1 ok
  1345. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  1346. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  1347. BL33 CHK: 0x000000ff ADDR 017a4000
  1348. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  1349. 00000000
  1350. emmc switch 2 ok
  1351. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1352. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  1353. 00000000
  1354. emmc switch 0 ok
  1355. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1356. reset...
  1357. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  1358. bl2_stage_init 0x01
  1359. bl2_stage_init 0x81
  1360. hw id: 0x0000 - pwm id 0x01
  1361. bl2_stage_init 0xc1
  1362. bl2_stage_init 0x02
  1363.  
  1364. L0:00000000
  1365. L1:20000703
  1366. L2:00008067
  1367. L3:14000000
  1368. B2:00402000
  1369. B1:e0f83180
  1370.  
  1371. TE: 87009
  1372.  
  1373. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  1374.  
  1375. Board ID = 12
  1376. Set A53 clk to 24M
  1377. Set A73 clk to 24M
  1378. Set clk81 to 24M
  1379. A53 clk: 1200 MHz
  1380. A73 clk: 1200 MHz
  1381. CLK81: 166.6M
  1382. smccc: 00019cc5
  1383. eMMC boot @ 1
  1384. sw8 s
  1385. board id: 12
  1386. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  1387. Get wrong ddr fw magic! Error!!
  1388. fw parse done
  1389. PIEI prepare done
  1390. 00000000
  1391. emmc switch 2 ok
  1392. 00000000
  1393. emmc switch 0 ok
  1394. NO find ddr boot_info from eMMC
  1395. fastboot data verify
  1396. result: 255
  1397. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  1398. LPDDR4 probe
  1399.  
  1400. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  1401. ddr clk to 1608MHz
  1402. 00000000
  1403. emmc switch 1 ok
  1404.  
  1405. dmc_version 0001
  1406. Check phy result
  1407. INFO : End of CA training
  1408. INFO : End of initialization
  1409. INFO : Training has run successfully!
  1410. Check phy result
  1411. INFO : End of initialization
  1412. INFO : End of read enable training
  1413. INFO : End of fine write leveling
  1414. INFO : End of read dq deskew training
  1415. INFO : End of MPR read delay center optimization
  1416. INFO : End of Write leveling coarse delay
  1417. INFO : End of read delay center optimization
  1418. INFO : Training has run successfully!
  1419. Check phy result
  1420. INFO : End of initialization
  1421. INFO : End of MPR read delay center optimization
  1422. INFO : End of write delay center optimization
  1423. INFO : End of read delay center optimization
  1424. INFO : End of max read latency training
  1425. INFO : Training has run successfully!
  1426. 1D training succeed
  1427. Check phy result
  1428. INFO : End of initialization
  1429. INFO : End of 2D read delay Voltage center optimization
  1430. INFO : End of 2D read delay Voltage center optimization
  1431. INFO : End of 2D write delay Voltage center optimization
  1432. INFO : End of 2D write delay Voltage center optimization
  1433. INFO : Training has run successfully!
  1434.  
  1435. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001d 0000001d 0000001b 0000001d 00000018 0000001c 0000001b 0000001b 0000001a 0000001c 0000001b 0000001c 0000001c 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001b 0000001d 0000001b 0000001b 0000001c 0000001b 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  1436. dram_vref_reg_value 0x 0000004d
  1437. 2D training succeed
  1438. auto size-- 65535DDR cs0 size: 2048MB
  1439. DDR cs1 size: 2048MB
  1440. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  1441. cs0 DataBus test pass
  1442. cs1 DataBus test pass
  1443. cs0 AddrBus test pass
  1444. cs1 AddrBus test pass
  1445.  
  1446. non-sec scramble use zero key
  1447. ddr scramble enabled
  1448.  
  1449. 100bdlr_step_size ps== 420
  1450. result report
  1451. boot times 0Enable ddr reg access
  1452. 00000000
  1453. emmc switch 3 ok
  1454. Authentication key not yet programmed
  1455. get rpmb counter error 0x00000007
  1456. 00000000
  1457. emmc switch 1 ok
  1458. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  1459. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  1460. BL33 CHK: 0x000000ff ADDR 017a4000
  1461. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  1462. 00000000
  1463. emmc switch 2 ok
  1464. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1465. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  1466. 00000000
  1467. emmc switch 0 ok
  1468. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1469. reset...
  1470. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  1471. bl2_stage_init 0x01
  1472. bl2_stage_init 0x81
  1473. hw id: 0x0000 - pwm id 0x01
  1474. bl2_stage_init 0xc1
  1475. bl2_stage_init 0x02
  1476.  
  1477. L0:00000000
  1478. L1:20000703
  1479. L2:00008067
  1480. L3:14000000
  1481. B2:00402000
  1482. B1:e0f83180
  1483.  
  1484. TE: 86870
  1485.  
  1486. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  1487.  
  1488. Board ID = 12
  1489. Set A53 clk to 24M
  1490. Set A73 clk to 24M
  1491. Set clk81 to 24M
  1492. A53 clk: 1200 MHz
  1493. A73 clk: 1200 MHz
  1494. CLK81: 166.6M
  1495. smccc: 00019c3a
  1496. eMMC boot @ 1
  1497. sw8 s
  1498. board id: 12
  1499. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  1500. Get wrong ddr fw magic! Error!!
  1501. fw parse done
  1502. PIEI prepare done
  1503. 00000000
  1504. emmc switch 2 ok
  1505. 00000000
  1506. emmc switch 0 ok
  1507. NO find ddr boot_info from eMMC
  1508. fastboot data verify
  1509. result: 255
  1510. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  1511. LPDDR4 probe
  1512.  
  1513. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  1514. ddr clk to 1608MHz
  1515. 00000000
  1516. emmc switch 1 ok
  1517.  
  1518. dmc_version 0001
  1519. Check phy result
  1520. INFO : End of CA training
  1521. INFO : End of initialization
  1522. INFO : Training has run successfully!
  1523. Check phy result
  1524. INFO : End of initialization
  1525. INFO : End of read enable training
  1526. INFO : End of fine write leveling
  1527. INFO : End of read dq deskew training
  1528. INFO : End of MPR read delay center optimization
  1529. INFO : End of Write leveling coarse delay
  1530. INFO : End of read delay center optimization
  1531. INFO : Training has run successfully!
  1532. Check phy result
  1533. INFO : End of initialization
  1534. INFO : End of MPR read delay center optimization
  1535. INFO : End of write delay center optimization
  1536. INFO : End of read delay center optimization
  1537. INFO : End of max read latency training
  1538. INFO : Training has run successfully!
  1539. 1D training succeed
  1540. Check phy result
  1541. INFO : End of initialization
  1542. INFO : End of 2D read delay Voltage center optimization
  1543. INFO : End of 2D read delay Voltage center optimization
  1544. INFO : End of 2D write delay Voltage center optimization
  1545. INFO : End of 2D write delay Voltage center optimization
  1546. INFO : Training has run successfully!
  1547.  
  1548. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c 0000001d 0000001c 0000001b 0000001d 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001d dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  1549. dram_vref_reg_value 0x 0000004d
  1550. 2D training succeed
  1551. auto size-- 65535DDR cs0 size: 2048MB
  1552. DDR cs1 size: 2048MB
  1553. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  1554. cs0 DataBus test pass
  1555. cs1 DataBus test pass
  1556. cs0 AddrBus test pass
  1557. cs1 AddrBus test pass
  1558.  
  1559. non-sec scramble use zero key
  1560. ddr scramble enabled
  1561.  
  1562. 100bdlr_step_size ps== 425
  1563. result report
  1564. boot times 0Enable ddr reg access
  1565. 00000000
  1566. emmc switch 3 ok
  1567. Authentication key not yet programmed
  1568. get rpmb counter error 0x00000007
  1569. 00000000
  1570. emmc switch 1 ok
  1571. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  1572. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  1573. BL33 CHK: 0x000000ff ADDR 017a4000
  1574. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  1575. 00000000
  1576. emmc switch 2 ok
  1577. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1578. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  1579. 00000000
  1580. emmc switch 0 ok
  1581. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1582. reset...
  1583. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  1584. bl2_stage_init 0x01
  1585. bl2_stage_init 0x81
  1586. hw id: 0x0000 - pwm id 0x01
  1587. bl2_stage_init 0xc1
  1588. bl2_stage_init 0x02
  1589.  
  1590. L0:00000000
  1591. L1:20000703
  1592. L2:00008067
  1593. L3:14000000
  1594. B2:00402000
  1595. B1:e0f83180
  1596.  
  1597. TE: 86862
  1598.  
  1599. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  1600.  
  1601. Board ID = 12
  1602. Set A53 clk to 24M
  1603. Set A73 clk to 24M
  1604. Set clk81 to 24M
  1605. A53 clk: 1200 MHz
  1606. A73 clk: 1200 MHz
  1607. CLK81: 166.6M
  1608. smccc: 00019c32
  1609. eMMC boot @ 1
  1610. sw8 s
  1611. board id: 12
  1612. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  1613. Get wrong ddr fw magic! Error!!
  1614. fw parse done
  1615. PIEI prepare done
  1616. 00000000
  1617. emmc switch 2 ok
  1618. 00000000
  1619. emmc switch 0 ok
  1620. NO find ddr boot_info from eMMC
  1621. fastboot data verify
  1622. result: 255
  1623. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  1624. LPDDR4 probe
  1625.  
  1626. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  1627. ddr clk to 1608MHz
  1628. 00000000
  1629. emmc switch 1 ok
  1630.  
  1631. dmc_version 0001
  1632. Check phy result
  1633. INFO : End of CA training
  1634. INFO : End of initialization
  1635. INFO : Training has run successfully!
  1636. Check phy result
  1637. INFO : End of initialization
  1638. INFO : End of read enable training
  1639. INFO : End of fine write leveling
  1640. INFO : End of read dq deskew training
  1641. INFO : End of MPR read delay center optimization
  1642. INFO : End of Write leveling coarse delay
  1643. INFO : End of read delay center optimization
  1644. INFO : Training has run successfully!
  1645. Check phy result
  1646. INFO : End of initialization
  1647. INFO : End of MPR read delay center optimization
  1648. INFO : End of write delay center optimization
  1649. INFO : End of read delay center optimization
  1650. INFO : End of max read latency training
  1651. INFO : Training has run successfully!
  1652. 1D training succeed
  1653. Check phy result
  1654. INFO : End of initialization
  1655. INFO : End of 2D read delay Voltage center optimization
  1656. INFO : End of 2D read delay Voltage center optimization
  1657. INFO : End of 2D write delay Voltage center optimization
  1658. INFO : End of 2D write delay Voltage center optimization
  1659. INFO : Training has run successfully!
  1660.  
  1661. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001b 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 00000019 00000019 0000001c 0000001a 0000001b 0000001b 0000001b 0000001a 0000001b 0000001b 0000001b 0000001b 0000001b 0000001a 0000001c 0000001a 0000001b 0000001b 0000001a 0000001a 0000001c 0000001b dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  1662. dram_vref_reg_value 0x 0000004d
  1663. 2D training succeed
  1664. auto size-- 65535DDR cs0 size: 2048MB
  1665. DDR cs1 size: 2048MB
  1666. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  1667. cs0 DataBus test pass
  1668. cs1 DataBus test pass
  1669. cs0 AddrBus test pass
  1670. cs1 AddrBus test pass
  1671.  
  1672. non-sec scramble use zero key
  1673. ddr scramble enabled
  1674.  
  1675. 100bdlr_step_size ps== 425
  1676. result report
  1677. boot times 0Enable ddr reg access
  1678. 00000000
  1679. emmc switch 3 ok
  1680. Authentication key not yet programmed
  1681. get rpmb counter error 0x00000007
  1682. 00000000
  1683. emmc switch 1 ok
  1684. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  1685. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  1686. BL33 CHK: 0x000000ff ADDR 017a4000
  1687. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  1688. 00000000
  1689. emmc switch 2 ok
  1690. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1691. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  1692. 00000000
  1693. emmc switch 0 ok
  1694. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1695. reset...
  1696. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  1697. bl2_stage_init 0x01
  1698. bl2_stage_init 0x81
  1699. hw id: 0x0000 - pwm id 0x01
  1700. bl2_stage_init 0xc1
  1701. bl2_stage_init 0x02
  1702.  
  1703. L0:00000000
  1704. L1:20000703
  1705. L2:00008067
  1706. L3:14000000
  1707. B2:00402000
  1708. B1:e0f83180
  1709.  
  1710. TE: 86870
  1711.  
  1712. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  1713.  
  1714. Board ID = 12
  1715. Set A53 clk to 24M
  1716. Set A73 clk to 24M
  1717. Set clk81 to 24M
  1718. A53 clk: 1200 MHz
  1719. A73 clk: 1200 MHz
  1720. CLK81: 166.6M
  1721. smccc: 00019c3a
  1722. eMMC boot @ 1
  1723. sw8 s
  1724. board id: 12
  1725. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  1726. Get wrong ddr fw magic! Error!!
  1727. fw parse done
  1728. PIEI prepare done
  1729. 00000000
  1730. emmc switch 2 ok
  1731. 00000000
  1732. emmc switch 0 ok
  1733. NO find ddr boot_info from eMMC
  1734. fastboot data verify
  1735. result: 255
  1736. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  1737. LPDDR4 probe
  1738.  
  1739. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  1740. ddr clk to 1608MHz
  1741. 00000000
  1742. emmc switch 1 ok
  1743.  
  1744. dmc_version 0001
  1745. Check phy result
  1746. INFO : End of CA training
  1747. INFO : End of initialization
  1748. INFO : Training has run successfully!
  1749. Check phy result
  1750. INFO : End of initialization
  1751. INFO : End of read enable training
  1752. INFO : End of fine write leveling
  1753. INFO : End of read dq deskew training
  1754. INFO : End of MPR read delay center optimization
  1755. INFO : End of Write leveling coarse delay
  1756. INFO : End of read delay center optimization
  1757. INFO : Training has run successfully!
  1758. Check phy result
  1759. INFO : End of initialization
  1760. INFO : End of MPR read delay center optimization
  1761. INFO : End of write delay center optimization
  1762. INFO : End of read delay center optimization
  1763. INFO : End of max read latency training
  1764. INFO : Training has run successfully!
  1765. 1D training succeed
  1766. Check phy result
  1767. INFO : End of initialization
  1768. INFO : End of 2D read delay Voltage center optimization
  1769. INFO : End of 2D read delay Voltage center optimization
  1770. INFO : End of 2D write delay Voltage center optimization
  1771. INFO : End of 2D write delay Voltage center optimization
  1772. INFO : Training has run successfully!
  1773.  
  1774. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001a 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c 0000001d 0000001c 0000001b 0000001e 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001d dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  1775. dram_vref_reg_value 0x 0000004d
  1776. 2D training succeed
  1777. auto size-- 65535DDR cs0 size: 2048MB
  1778. DDR cs1 size: 2048MB
  1779. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  1780. cs0 DataBus test pass
  1781. cs1 DataBus test pass
  1782. cs0 AddrBus test pass
  1783. cs1 AddrBus test pass
  1784.  
  1785. non-sec scramble use zero key
  1786. ddr scramble enabled
  1787.  
  1788. 100bdlr_step_size ps== 420
  1789. result report
  1790. boot times 0Enable ddr reg access
  1791. 00000000
  1792. emmc switch 3 ok
  1793. Authentication key not yet programmed
  1794. get rpmb counter error 0x00000007
  1795. 00000000
  1796. emmc switch 1 ok
  1797. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  1798. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  1799. BL33 CHK: 0x000000ff ADDR 017a4000
  1800. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  1801. 00000000
  1802. emmc switch 2 ok
  1803. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1804. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  1805. 00000000
  1806. emmc switch 0 ok
  1807. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1808. reset...
  1809. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  1810. bl2_stage_init 0x01
  1811. bl2_stage_init 0x81
  1812. hw id: 0x0000 - pwm id 0x01
  1813. bl2_stage_init 0xc1
  1814. bl2_stage_init 0x02
  1815.  
  1816. L0:00000000
  1817. L1:20000703
  1818. L2:00008067
  1819. L3:14000000
  1820. B2:00402000
  1821. B1:e0f83180
  1822.  
  1823. TE: 87069
  1824.  
  1825. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  1826.  
  1827. Board ID = 12
  1828. Set A53 clk to 24M
  1829. Set A73 clk to 24M
  1830. Set clk81 to 24M
  1831. A53 clk: 1200 MHz
  1832. A73 clk: 1200 MHz
  1833. CLK81: 166.6M
  1834. smccc: 00019d01
  1835. eMMC boot @ 1
  1836. sw8 s
  1837. board id: 12
  1838. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  1839. Get wrong ddr fw magic! Error!!
  1840. fw parse done
  1841. PIEI prepare done
  1842. 00000000
  1843. emmc switch 2 ok
  1844. 00000000
  1845. emmc switch 0 ok
  1846. NO find ddr boot_info from eMMC
  1847. fastboot data verify
  1848. result: 255
  1849. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  1850. LPDDR4 probe
  1851.  
  1852. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  1853. ddr clk to 1608MHz
  1854. 00000000
  1855. emmc switch 1 ok
  1856.  
  1857. dmc_version 0001
  1858. Check phy result
  1859. INFO : End of CA training
  1860. INFO : End of initialization
  1861. INFO : Training has run successfully!
  1862. Check phy result
  1863. INFO : End of initialization
  1864. INFO : End of read enable training
  1865. INFO : End of fine write leveling
  1866. INFO : End of read dq deskew training
  1867. INFO : End of MPR read delay center optimization
  1868. INFO : End of Write leveling coarse delay
  1869. INFO : End of read delay center optimization
  1870. INFO : Training has run successfully!
  1871. Check phy result
  1872. INFO : End of initialization
  1873. INFO : End of MPR read delay center optimization
  1874. INFO : End of write delay center optimization
  1875. INFO : End of read delay center optimization
  1876. INFO : End of max read latency training
  1877. INFO : Training has run successfully!
  1878. 1D training succeed
  1879. Check phy result
  1880. INFO : End of initialization
  1881. INFO : End of 2D read delay Voltage center optimization
  1882. INFO : End of 2D read delay Voltage center optimization
  1883. INFO : End of 2D write delay Voltage center optimization
  1884. INFO : End of 2D write delay Voltage center optimization
  1885. INFO : Training has run successfully!
  1886.  
  1887. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001c 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 0000001a 00000019 0000001c 0000001a 0000001b 0000001b 0000001c 0000001b 0000001c 0000001c 0000001c 0000001c 0000001b 0000001a 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  1888. dram_vref_reg_value 0x 0000004d
  1889. 2D training succeed
  1890. auto size-- 65535DDR cs0 size: 2048MB
  1891. DDR cs1 size: 2048MB
  1892. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  1893. cs0 DataBus test pass
  1894. cs1 DataBus test pass
  1895. cs0 AddrBus test pass
  1896. cs1 AddrBus test pass
  1897.  
  1898. non-sec scramble use zero key
  1899. ddr scramble enabled
  1900.  
  1901. 100bdlr_step_size ps== 420
  1902. result report
  1903. boot times 0Enable ddr reg access
  1904. 00000000
  1905. emmc switch 3 ok
  1906. Authentication key not yet programmed
  1907. get rpmb counter error 0x00000007
  1908. 00000000
  1909. emmc switch 1 ok
  1910. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  1911. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  1912. BL33 CHK: 0x000000ff ADDR 017a4000
  1913. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  1914. 00000000
  1915. emmc switch 2 ok
  1916. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1917. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  1918. 00000000
  1919. emmc switch 0 ok
  1920. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  1921. reset...
  1922. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  1923. bl2_stage_init 0x01
  1924. bl2_stage_init 0x81
  1925. hw id: 0x0000 - pwm id 0x01
  1926. bl2_stage_init 0xc1
  1927. bl2_stage_init 0x02
  1928.  
  1929. L0:00000000
  1930. L1:20000703
  1931. L2:00008067
  1932. L3:14000000
  1933. B2:00402000
  1934. B1:e0f83180
  1935.  
  1936. TE: 86870
  1937.  
  1938. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  1939.  
  1940. Board ID = 12
  1941. Set A53 clk to 24M
  1942. Set A73 clk to 24M
  1943. Set clk81 to 24M
  1944. A53 clk: 1200 MHz
  1945. A73 clk: 1200 MHz
  1946. CLK81: 166.6M
  1947. smccc: 00019c3a
  1948. eMMC boot @ 1
  1949. sw8 s
  1950. board id: 12
  1951. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  1952. Get wrong ddr fw magic! Error!!
  1953. fw parse done
  1954. PIEI prepare done
  1955. 00000000
  1956. emmc switch 2 ok
  1957. 00000000
  1958. emmc switch 0 ok
  1959. NO find ddr boot_info from eMMC
  1960. fastboot data verify
  1961. result: 255
  1962. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  1963. LPDDR4 probe
  1964.  
  1965. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  1966. ddr clk to 1608MHz
  1967. 00000000
  1968. emmc switch 1 ok
  1969.  
  1970. dmc_version 0001
  1971. Check phy result
  1972. INFO : End of CA training
  1973. INFO : End of initialization
  1974. INFO : Training has run successfully!
  1975. Check phy result
  1976. INFO : End of initialization
  1977. INFO : End of read enable training
  1978. INFO : End of fine write leveling
  1979. INFO : End of read dq deskew training
  1980. INFO : End of MPR read delay center optimization
  1981. INFO : End of Write leveling coarse delay
  1982. INFO : End of read delay center optimization
  1983. INFO : Training has run successfully!
  1984. Check phy result
  1985. INFO : End of initialization
  1986. INFO : End of MPR read delay center optimization
  1987. INFO : End of write delay center optimization
  1988. INFO : End of read delay center optimization
  1989. INFO : End of max read latency training
  1990. INFO : Training has run successfully!
  1991. 1D training succeed
  1992. Check phy result
  1993. INFO : End of initialization
  1994. INFO : End of 2D read delay Voltage center optimization
  1995. INFO : End of 2D read delay Voltage center optimization
  1996. INFO : End of 2D write delay Voltage center optimization
  1997. INFO : End of 2D write delay Voltage center optimization
  1998. INFO : Training has run successfully!
  1999.  
  2000. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001b 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 00000019 00000019 0000001b 0000001a 0000001b 0000001b 0000001b 00000019 0000001b 0000001b 0000001b 0000001b 0000001a 0000001a 0000001c 0000001a 0000001b 0000001b 0000001a 0000001b 0000001c 0000001b dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  2001. dram_vref_reg_value 0x 0000004e
  2002. 2D training succeed
  2003. auto size-- 65535DDR cs0 size: 2048MB
  2004. DDR cs1 size: 2048MB
  2005. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  2006. cs0 DataBus test pass
  2007. cs1 DataBus test pass
  2008. cs0 AddrBus test pass
  2009. cs1 AddrBus test pass
  2010.  
  2011. non-sec scramble use zero key
  2012. ddr scramble enabled
  2013.  
  2014. 100bdlr_step_size ps== 420
  2015. result report
  2016. boot times 0Enable ddr reg access
  2017. 00000000
  2018. emmc switch 3 ok
  2019. Authentication key not yet programmed
  2020. get rpmb counter error 0x00000007
  2021. 00000000
  2022. emmc switch 1 ok
  2023. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  2024. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  2025. BL33 CHK: 0x000000ff ADDR 017a4000
  2026. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  2027. 00000000
  2028. emmc switch 2 ok
  2029. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2030. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  2031. 00000000
  2032. emmc switch 0 ok
  2033. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2034. reset...
  2035. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  2036. bl2_stage_init 0x01
  2037. bl2_stage_init 0x81
  2038. hw id: 0x0000 - pwm id 0x01
  2039. bl2_stage_init 0xc1
  2040. bl2_stage_init 0x02
  2041.  
  2042. L0:00000000
  2043. L1:20000703
  2044. L2:00008067
  2045. L3:14000000
  2046. B2:00402000
  2047. B1:e0f83180
  2048.  
  2049. TE: 87009
  2050.  
  2051. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  2052.  
  2053. Board ID = 12
  2054. Set A53 clk to 24M
  2055. Set A73 clk to 24M
  2056. Set clk81 to 24M
  2057. A53 clk: 1200 MHz
  2058. A73 clk: 1200 MHz
  2059. CLK81: 166.6M
  2060. smccc: 00019cc5
  2061. eMMC boot @ 1
  2062. sw8 s
  2063. board id: 12
  2064. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  2065. Get wrong ddr fw magic! Error!!
  2066. fw parse done
  2067. PIEI prepare done
  2068. 00000000
  2069. emmc switch 2 ok
  2070. 00000000
  2071. emmc switch 0 ok
  2072. NO find ddr boot_info from eMMC
  2073. fastboot data verify
  2074. result: 255
  2075. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  2076. LPDDR4 probe
  2077.  
  2078. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  2079. ddr clk to 1608MHz
  2080. 00000000
  2081. emmc switch 1 ok
  2082.  
  2083. dmc_version 0001
  2084. Check phy result
  2085. INFO : End of CA training
  2086. INFO : End of initialization
  2087. INFO : Training has run successfully!
  2088. Check phy result
  2089. INFO : End of initialization
  2090. INFO : End of read enable training
  2091. INFO : End of fine write leveling
  2092. INFO : End of read dq deskew training
  2093. INFO : End of MPR read delay center optimization
  2094. INFO : End of Write leveling coarse delay
  2095. INFO : End of read delay center optimization
  2096. INFO : Training has run successfully!
  2097. Check phy result
  2098. INFO : End of initialization
  2099. INFO : End of MPR read delay center optimization
  2100. INFO : End of write delay center optimization
  2101. INFO : End of read delay center optimization
  2102. INFO : End of max read latency training
  2103. INFO : Training has run successfully!
  2104. 1D training succeed
  2105. Check phy result
  2106. INFO : End of initialization
  2107. INFO : End of 2D read delay Voltage center optimization
  2108. INFO : End of 2D read delay Voltage center optimization
  2109. INFO : End of 2D write delay Voltage center optimization
  2110. INFO : End of 2D write delay Voltage center optimization
  2111. INFO : Training has run successfully!
  2112.  
  2113. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c 0000001d 0000001c 0000001b 0000001e 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  2114. dram_vref_reg_value 0x 0000004d
  2115. 2D training succeed
  2116. auto size-- 65535DDR cs0 size: 2048MB
  2117. DDR cs1 size: 2048MB
  2118. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  2119. cs0 DataBus test pass
  2120. cs1 DataBus test pass
  2121. cs0 AddrBus test pass
  2122. cs1 AddrBus test pass
  2123.  
  2124. non-sec scramble use zero key
  2125. ddr scramble enabled
  2126.  
  2127. 100bdlr_step_size ps== 420
  2128. result report
  2129. boot times 0Enable ddr reg access
  2130. 00000000
  2131. emmc switch 3 ok
  2132. Authentication key not yet programmed
  2133. get rpmb counter error 0x00000007
  2134. 00000000
  2135. emmc switch 1 ok
  2136. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  2137. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  2138. BL33 CHK: 0x000000ff ADDR 017a4000
  2139. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  2140. 00000000
  2141. emmc switch 2 ok
  2142. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2143. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  2144. 00000000
  2145. emmc switch 0 ok
  2146. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2147. reset...
  2148. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  2149. bl2_stage_init 0x01
  2150. bl2_stage_init 0x81
  2151. hw id: 0x0000 - pwm id 0x01
  2152. bl2_stage_init 0xc1
  2153. bl2_stage_init 0x02
  2154.  
  2155. L0:00000000
  2156. L1:20000703
  2157. L2:00008067
  2158. L3:14000000
  2159. B2:00402000
  2160. B1:e0f83180
  2161.  
  2162. TE: 86870
  2163.  
  2164. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  2165.  
  2166. Board ID = 12
  2167. Set A53 clk to 24M
  2168. Set A73 clk to 24M
  2169. Set clk81 to 24M
  2170. A53 clk: 1200 MHz
  2171. A73 clk: 1200 MHz
  2172. CLK81: 166.6M
  2173. smccc: 00019c3a
  2174. eMMC boot @ 1
  2175. sw8 s
  2176. board id: 12
  2177. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  2178. Get wrong ddr fw magic! Error!!
  2179. fw parse done
  2180. PIEI prepare done
  2181. 00000000
  2182. emmc switch 2 ok
  2183. 00000000
  2184. emmc switch 0 ok
  2185. NO find ddr boot_info from eMMC
  2186. fastboot data verify
  2187. result: 255
  2188. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  2189. LPDDR4 probe
  2190.  
  2191. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  2192. ddr clk to 1608MHz
  2193. 00000000
  2194. emmc switch 1 ok
  2195.  
  2196. dmc_version 0001
  2197. Check phy result
  2198. INFO : End of CA training
  2199. INFO : End of initialization
  2200. INFO : Training has run successfully!
  2201. Check phy result
  2202. INFO : End of initialization
  2203. INFO : End of read enable training
  2204. INFO : End of fine write leveling
  2205. INFO : End of read dq deskew training
  2206. INFO : End of MPR read delay center optimization
  2207. INFO : End of Write leveling coarse delay
  2208. INFO : End of read delay center optimization
  2209. INFO : Training has run successfully!
  2210. Check phy result
  2211. INFO : End of initialization
  2212. INFO : End of MPR read delay center optimization
  2213. INFO : End of write delay center optimization
  2214. INFO : End of read delay center optimization
  2215. INFO : End of max read latency training
  2216. INFO : Training has run successfully!
  2217. 1D training succeed
  2218. Check phy result
  2219. INFO : End of initialization
  2220. INFO : End of 2D read delay Voltage center optimization
  2221. INFO : End of 2D read delay Voltage center optimization
  2222. INFO : End of 2D write delay Voltage center optimization
  2223. INFO : End of 2D write delay Voltage center optimization
  2224. INFO : Training has run successfully!
  2225.  
  2226. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001a 0000001c 00000017 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001c 0000001c 0000001b 0000001a 0000001b 0000001b 0000001b 0000001c 0000001a 0000001a 0000001c 0000001a 0000001b 0000001b 0000001a 0000001b 0000001c 0000001b dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  2227. dram_vref_reg_value 0x 0000004d
  2228. 2D training succeed
  2229. auto size-- 65535DDR cs0 size: 2048MB
  2230. DDR cs1 size: 2048MB
  2231. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  2232. cs0 DataBus test pass
  2233. cs1 DataBus test pass
  2234. cs0 AddrBus test pass
  2235. cs1 AddrBus test pass
  2236.  
  2237. non-sec scramble use zero key
  2238. ddr scramble enabled
  2239.  
  2240. 100bdlr_step_size ps== 420
  2241. result report
  2242. boot times 0Enable ddr reg access
  2243. 00000000
  2244. emmc switch 3 ok
  2245. Authentication key not yet programmed
  2246. get rpmb counter error 0x00000007
  2247. 00000000
  2248. emmc switch 1 ok
  2249. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  2250. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  2251. BL33 CHK: 0x000000ff ADDR 017a4000
  2252. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  2253. 00000000
  2254. emmc switch 2 ok
  2255. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2256. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  2257. 00000000
  2258. emmc switch 0 ok
  2259. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2260. reset...
  2261. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  2262. bl2_stage_init 0x01
  2263. bl2_stage_init 0x81
  2264. hw id: 0x0000 - pwm id 0x01
  2265. bl2_stage_init 0xc1
  2266. bl2_stage_init 0x02
  2267.  
  2268. L0:00000000
  2269. L1:20000703
  2270. L2:00008067
  2271. L3:14000000
  2272. B2:00402000
  2273. B1:e0f83180
  2274.  
  2275. TE: 86862
  2276.  
  2277. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  2278.  
  2279. Board ID = 12
  2280. Set A53 clk to 24M
  2281. Set A73 clk to 24M
  2282. Set clk81 to 24M
  2283. A53 clk: 1200 MHz
  2284. A73 clk: 1200 MHz
  2285. CLK81: 166.6M
  2286. smccc: 00019c31
  2287. eMMC boot @ 1
  2288. sw8 s
  2289. board id: 12
  2290. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  2291. Get wrong ddr fw magic! Error!!
  2292. fw parse done
  2293. PIEI prepare done
  2294. 00000000
  2295. emmc switch 2 ok
  2296. 00000000
  2297. emmc switch 0 ok
  2298. NO find ddr boot_info from eMMC
  2299. fastboot data verify
  2300. result: 255
  2301. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  2302. LPDDR4 probe
  2303.  
  2304. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  2305. ddr clk to 1608MHz
  2306. 00000000
  2307. emmc switch 1 ok
  2308.  
  2309. dmc_version 0001
  2310. Check phy result
  2311. INFO : End of CA training
  2312. INFO : End of initialization
  2313. INFO : Training has run successfully!
  2314. Check phy result
  2315. INFO : End of initialization
  2316. INFO : End of read enable training
  2317. INFO : End of fine write leveling
  2318. INFO : End of read dq deskew training
  2319. INFO : End of MPR read delay center optimization
  2320. INFO : End of Write leveling coarse delay
  2321. INFO : End of read delay center optimization
  2322. INFO : Training has run successfully!
  2323. Check phy result
  2324. INFO : End of initialization
  2325. INFO : End of MPR read delay center optimization
  2326. INFO : End of write delay center optimization
  2327. INFO : End of read delay center optimization
  2328. INFO : End of max read latency training
  2329. INFO : Training has run successfully!
  2330. 1D training succeed
  2331. Check phy result
  2332. INFO : End of initialization
  2333. INFO : End of 2D read delay Voltage center optimization
  2334. INFO : End of 2D read delay Voltage center optimization
  2335. INFO : End of 2D write delay Voltage center optimization
  2336. INFO : End of 2D write delay Voltage center optimization
  2337. INFO : Training has run successfully!
  2338.  
  2339. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001c 0000001c 0000001b 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001a 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  2340. dram_vref_reg_value 0x 0000004d
  2341. 2D training succeed
  2342. auto size-- 65535DDR cs0 size: 2048MB
  2343. DDR cs1 size: 2048MB
  2344. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  2345. cs0 DataBus test pass
  2346. cs1 DataBus test pass
  2347. cs0 AddrBus test pass
  2348. cs1 AddrBus test pass
  2349.  
  2350. non-sec scramble use zero key
  2351. ddr scramble enabled
  2352.  
  2353. 100bdlr_step_size ps== 431
  2354. result report
  2355. boot times 0Enable ddr reg access
  2356. 00000000
  2357. emmc switch 3 ok
  2358. Authentication key not yet programmed
  2359. get rpmb counter error 0x00000007
  2360. 00000000
  2361. emmc switch 1 ok
  2362. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  2363. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  2364. BL33 CHK: 0x000000ff ADDR 017a4000
  2365. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  2366. 00000000
  2367. emmc switch 2 ok
  2368. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2369. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  2370. 00000000
  2371. emmc switch 0 ok
  2372. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2373. reset...
  2374. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  2375. bl2_stage_init 0x01
  2376. bl2_stage_init 0x81
  2377. hw id: 0x0000 - pwm id 0x01
  2378. bl2_stage_init 0xc1
  2379. bl2_stage_init 0x02
  2380.  
  2381. L0:00000000
  2382. L1:20000703
  2383. L2:00008067
  2384. L3:14000000
  2385. B2:00402000
  2386. B1:e0f83180
  2387.  
  2388. TE: 86870
  2389.  
  2390. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  2391.  
  2392. Board ID = 12
  2393. Set A53 clk to 24M
  2394. Set A73 clk to 24M
  2395. Set clk81 to 24M
  2396. A53 clk: 1200 MHz
  2397. A73 clk: 1200 MHz
  2398. CLK81: 166.6M
  2399. smccc: 00019c3a
  2400. eMMC boot @ 1
  2401. sw8 s
  2402. board id: 12
  2403. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  2404. Get wrong ddr fw magic! Error!!
  2405. fw parse done
  2406. PIEI prepare done
  2407. 00000000
  2408. emmc switch 2 ok
  2409. 00000000
  2410. emmc switch 0 ok
  2411. NO find ddr boot_info from eMMC
  2412. fastboot data verify
  2413. result: 255
  2414. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  2415. LPDDR4 probe
  2416.  
  2417. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  2418. ddr clk to 1608MHz
  2419. 00000000
  2420. emmc switch 1 ok
  2421.  
  2422. dmc_version 0001
  2423. Check phy result
  2424. INFO : End of CA training
  2425. INFO : End of initialization
  2426. INFO : Training has run successfully!
  2427. Check phy result
  2428. INFO : End of initialization
  2429. INFO : End of read enable training
  2430. INFO : End of fine write leveling
  2431. INFO : End of read dq deskew training
  2432. INFO : End of MPR read delay center optimization
  2433. INFO : End of Write leveling coarse delay
  2434. INFO : End of read delay center optimization
  2435. INFO : Training has run successfully!
  2436. Check phy result
  2437. INFO : End of initialization
  2438. INFO : End of MPR read delay center optimization
  2439. INFO : End of write delay center optimization
  2440. INFO : End of read delay center optimization
  2441. INFO : End of max read latency training
  2442. INFO : Training has run successfully!
  2443. 1D training succeed
  2444. Check phy result
  2445. INFO : End of initialization
  2446. INFO : End of 2D read delay Voltage center optimization
  2447. INFO : End of 2D read delay Voltage center optimization
  2448. INFO : End of 2D write delay Voltage center optimization
  2449. INFO : End of 2D write delay Voltage center optimization
  2450. INFO : Training has run successfully!
  2451.  
  2452. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001c 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 00000019 00000019 0000001c 0000001a 0000001b 0000001b 0000001b 0000001a 0000001b 0000001c 0000001b 0000001b 0000001a 0000001a 0000001c 0000001a 0000001b 0000001b 0000001a 0000001b 0000001c 0000001b dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  2453. dram_vref_reg_value 0x 0000004e
  2454. 2D training succeed
  2455. auto size-- 65535DDR cs0 size: 2048MB
  2456. DDR cs1 size: 2048MB
  2457. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  2458. cs0 DataBus test pass
  2459. cs1 DataBus test pass
  2460. cs0 AddrBus test pass
  2461. cs1 AddrBus test pass
  2462.  
  2463. non-sec scramble use zero key
  2464. ddr scramble enabled
  2465.  
  2466. 100bdlr_step_size ps== 420
  2467. result report
  2468. boot times 0Enable ddr reg access
  2469. 00000000
  2470. emmc switch 3 ok
  2471. Authentication key not yet programmed
  2472. get rpmb counter error 0x00000007
  2473. 00000000
  2474. emmc switch 1 ok
  2475. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  2476. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  2477. BL33 CHK: 0x000000ff ADDR 017a4000
  2478. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  2479. 00000000
  2480. emmc switch 2 ok
  2481. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2482. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  2483. 00000000
  2484. emmc switch 0 ok
  2485. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2486. reset...
  2487. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  2488. bl2_stage_init 0x01
  2489. bl2_stage_init 0x81
  2490. hw id: 0x0000 - pwm id 0x01
  2491. bl2_stage_init 0xc1
  2492. bl2_stage_init 0x02
  2493.  
  2494. L0:00000000
  2495. L1:20000703
  2496. L2:00008067
  2497. L3:14000000
  2498. B2:00402000
  2499. B1:e0f83180
  2500.  
  2501. TE: 86871
  2502.  
  2503. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  2504.  
  2505. Board ID = 12
  2506. Set A53 clk to 24M
  2507. Set A73 clk to 24M
  2508. Set clk81 to 24M
  2509. A53 clk: 1200 MHz
  2510. A73 clk: 1200 MHz
  2511. CLK81: 166.6M
  2512. smccc: 00019c3b
  2513. eMMC boot @ 1
  2514. sw8 s
  2515. board id: 12
  2516. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  2517. Get wrong ddr fw magic! Error!!
  2518. fw parse done
  2519. PIEI prepare done
  2520. 00000000
  2521. emmc switch 2 ok
  2522. 00000000
  2523. emmc switch 0 ok
  2524. NO find ddr boot_info from eMMC
  2525. fastboot data verify
  2526. result: 255
  2527. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  2528. LPDDR4 probe
  2529.  
  2530. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  2531. ddr clk to 1608MHz
  2532. 00000000
  2533. emmc switch 1 ok
  2534.  
  2535. dmc_version 0001
  2536. Check phy result
  2537. INFO : End of CA training
  2538. INFO : End of initialization
  2539. INFO : Training has run successfully!
  2540. Check phy result
  2541. INFO : End of initialization
  2542. INFO : End of read enable training
  2543. INFO : End of fine write leveling
  2544. INFO : End of read dq deskew training
  2545. INFO : End of MPR read delay center optimization
  2546. INFO : End of Write leveling coarse delay
  2547. INFO : End of read delay center optimization
  2548. INFO : Training has run successfully!
  2549. Check phy result
  2550. INFO : End of initialization
  2551. INFO : End of MPR read delay center optimization
  2552. INFO : End of write delay center optimization
  2553. INFO : End of read delay center optimization
  2554. INFO : End of max read latency training
  2555. INFO : Training has run successfully!
  2556. 1D training succeed
  2557. Check phy result
  2558. INFO : End of initialization
  2559. INFO : End of 2D read delay Voltage center optimization
  2560. INFO : End of 2D read delay Voltage center optimization
  2561. INFO : End of 2D write delay Voltage center optimization
  2562. INFO : End of 2D write delay Voltage center optimization
  2563. INFO : Training has run successfully!
  2564.  
  2565. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001c 0000001b 0000001c 0000001c 0000001c 0000001c 0000001b 0000001b 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  2566. dram_vref_reg_value 0x 0000004d
  2567. 2D training succeed
  2568. auto size-- 65535DDR cs0 size: 2048MB
  2569. DDR cs1 size: 2048MB
  2570. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  2571. cs0 DataBus test pass
  2572. cs1 DataBus test pass
  2573. cs0 AddrBus test pass
  2574. cs1 AddrBus test pass
  2575.  
  2576. non-sec scramble use zero key
  2577. ddr scramble enabled
  2578.  
  2579. 100bdlr_step_size ps== 420
  2580. result report
  2581. boot times 0Enable ddr reg access
  2582. 00000000
  2583. emmc switch 3 ok
  2584. Authentication key not yet programmed
  2585. get rpmb counter error 0x00000007
  2586. 00000000
  2587. emmc switch 1 ok
  2588. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  2589. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  2590. BL33 CHK: 0x000000ff ADDR 017a4000
  2591. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  2592. 00000000
  2593. emmc switch 2 ok
  2594. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2595. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  2596. 00000000
  2597. emmc switch 0 ok
  2598. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2599. reset...
  2600. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  2601. bl2_stage_init 0x01
  2602. bl2_stage_init 0x81
  2603. hw id: 0x0000 - pwm id 0x01
  2604. bl2_stage_init 0xc1
  2605. bl2_stage_init 0x02
  2606.  
  2607. L0:00000000
  2608. L1:20000703
  2609. L2:00008067
  2610. L3:14000000
  2611. B2:00402000
  2612. B1:e0f83180
  2613.  
  2614. TE: 87000
  2615.  
  2616. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  2617.  
  2618. Board ID = 12
  2619. Set A53 clk to 24M
  2620. Set A73 clk to 24M
  2621. Set clk81 to 24M
  2622. A53 clk: 1200 MHz
  2623. A73 clk: 1200 MHz
  2624. CLK81: 166.6M
  2625. smccc: 00019cbc
  2626. eMMC boot @ 1
  2627. sw8 s
  2628. board id: 12
  2629. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  2630. Get wrong ddr fw magic! Error!!
  2631. fw parse done
  2632. PIEI prepare done
  2633. 00000000
  2634. emmc switch 2 ok
  2635. 00000000
  2636. emmc switch 0 ok
  2637. NO find ddr boot_info from eMMC
  2638. fastboot data verify
  2639. result: 255
  2640. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  2641. LPDDR4 probe
  2642.  
  2643. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  2644. ddr clk to 1608MHz
  2645. 00000000
  2646. emmc switch 1 ok
  2647.  
  2648. dmc_version 0001
  2649. Check phy result
  2650. INFO : End of CA training
  2651. INFO : End of initialization
  2652. INFO : Training has run successfully!
  2653. Check phy result
  2654. INFO : End of initialization
  2655. INFO : End of read enable training
  2656. INFO : End of fine write leveling
  2657. INFO : End of read dq deskew training
  2658. INFO : End of MPR read delay center optimization
  2659. INFO : End of Write leveling coarse delay
  2660. INFO : End of read delay center optimization
  2661. INFO : Training has run successfully!
  2662. Check phy result
  2663. INFO : End of initialization
  2664. INFO : End of MPR read delay center optimization
  2665. INFO : End of write delay center optimization
  2666. INFO : End of read delay center optimization
  2667. INFO : End of max read latency training
  2668. INFO : Training has run successfully!
  2669. 1D training succeed
  2670. Check phy result
  2671. INFO : End of initialization
  2672. INFO : End of 2D read delay Voltage center optimization
  2673. INFO : End of 2D read delay Voltage center optimization
  2674. INFO : End of 2D write delay Voltage center optimization
  2675. INFO : End of 2D write delay Voltage center optimization
  2676. INFO : Training has run successfully!
  2677.  
  2678. soc_vref_reg_value 0x 0000001b 0000001b 0000001d 0000001c 0000001c 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001c 0000001b 0000001c 0000001c 0000001c 0000001d 0000001b 0000001b 0000001e 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  2679. dram_vref_reg_value 0x 0000004d
  2680. 2D training succeed
  2681. auto size-- 65535DDR cs0 size: 2048MB
  2682. DDR cs1 size: 2048MB
  2683. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  2684. cs0 DataBus test pass
  2685. cs1 DataBus test pass
  2686. cs0 AddrBus test pass
  2687. cs1 AddrBus test pass
  2688.  
  2689. non-sec scramble use zero key
  2690. ddr scramble enabled
  2691.  
  2692. 100bdlr_step_size ps== 420
  2693. result report
  2694. boot times 0Enable ddr reg access
  2695. 00000000
  2696. emmc switch 3 ok
  2697. Authentication key not yet programmed
  2698. get rpmb counter error 0x00000007
  2699. 00000000
  2700. emmc switch 1 ok
  2701. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  2702. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  2703. BL33 CHK: 0x000000ff ADDR 017a4000
  2704. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  2705. 00000000
  2706. emmc switch 2 ok
  2707. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2708. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  2709. 00000000
  2710. emmc switch 0 ok
  2711. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2712. reset...
  2713. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  2714. bl2_stage_init 0x01
  2715. bl2_stage_init 0x81
  2716. hw id: 0x0000 - pwm id 0x01
  2717. bl2_stage_init 0xc1
  2718. bl2_stage_init 0x02
  2719.  
  2720. L0:00000000
  2721. L1:20000703
  2722. L2:00008067
  2723. L3:14000000
  2724. B2:00402000
  2725. B1:e0f83180
  2726.  
  2727. TE: 86871
  2728.  
  2729. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  2730.  
  2731. Board ID = 12
  2732. Set A53 clk to 24M
  2733. Set A73 clk to 24M
  2734. Set clk81 to 24M
  2735. A53 clk: 1200 MHz
  2736. A73 clk: 1200 MHz
  2737. CLK81: 166.6M
  2738. smccc: 00019c3b
  2739. eMMC boot @ 1
  2740. sw8 s
  2741. board id: 12
  2742. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  2743. Get wrong ddr fw magic! Error!!
  2744. fw parse done
  2745. PIEI prepare done
  2746. 00000000
  2747. emmc switch 2 ok
  2748. 00000000
  2749. emmc switch 0 ok
  2750. NO find ddr boot_info from eMMC
  2751. fastboot data verify
  2752. result: 255
  2753. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  2754. LPDDR4 probe
  2755.  
  2756. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  2757. ddr clk to 1608MHz
  2758. 00000000
  2759. emmc switch 1 ok
  2760.  
  2761. dmc_version 0001
  2762. Check phy result
  2763. INFO : End of CA training
  2764. INFO : End of initialization
  2765. INFO : Training has run successfully!
  2766. Check phy result
  2767. INFO : End of initialization
  2768. INFO : End of read enable training
  2769. INFO : End of fine write leveling
  2770. INFO : End of read dq deskew training
  2771. INFO : End of MPR read delay center optimization
  2772. INFO : End of Write leveling coarse delay
  2773. INFO : End of read delay center optimization
  2774. INFO : Training has run successfully!
  2775. Check phy result
  2776. INFO : End of initialization
  2777. INFO : End of MPR read delay center optimization
  2778. INFO : End of write delay center optimization
  2779. INFO : End of read delay center optimization
  2780. INFO : End of max read latency training
  2781. INFO : Training has run successfully!
  2782. 1D training succeed
  2783. Check phy result
  2784. INFO : End of initialization
  2785. INFO : End of 2D read delay Voltage center optimization
  2786. INFO : End of 2D read delay Voltage center optimization
  2787. INFO : End of 2D write delay Voltage center optimization
  2788. INFO : End of 2D write delay Voltage center optimization
  2789. INFO : Training has run successfully!
  2790.  
  2791. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001c 0000001c 0000001b 0000001a 0000001b 0000001b 0000001b 0000001b 0000001b 0000001a 0000001c 0000001a 0000001b 0000001b 0000001a 0000001b 0000001c 0000001b dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  2792. dram_vref_reg_value 0x 0000004d
  2793. 2D training succeed
  2794. auto size-- 65535DDR cs0 size: 2048MB
  2795. DDR cs1 size: 2048MB
  2796. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  2797. cs0 DataBus test pass
  2798. cs1 DataBus test pass
  2799. cs0 AddrBus test pass
  2800. cs1 AddrBus test pass
  2801.  
  2802. non-sec scramble use zero key
  2803. ddr scramble enabled
  2804.  
  2805. 100bdlr_step_size ps== 420
  2806. result report
  2807. boot times 0Enable ddr reg access
  2808. 00000000
  2809. emmc switch 3 ok
  2810. Authentication key not yet programmed
  2811. get rpmb counter error 0x00000007
  2812. 00000000
  2813. emmc switch 1 ok
  2814. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  2815. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  2816. BL33 CHK: 0x000000ff ADDR 017a4000
  2817. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  2818. 00000000
  2819. emmc switch 2 ok
  2820. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2821. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  2822. 00000000
  2823. emmc switch 0 ok
  2824. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2825. reset...
  2826. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  2827. bl2_stage_init 0x01
  2828. bl2_stage_init 0x81
  2829. hw id: 0x0000 - pwm id 0x01
  2830. bl2_stage_init 0xc1
  2831. bl2_stage_init 0x02
  2832.  
  2833. L0:00000000
  2834. L1:20000703
  2835. L2:00008067
  2836. L3:14000000
  2837. B2:00402000
  2838. B1:e0f83180
  2839.  
  2840. TE: 86870
  2841.  
  2842. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  2843.  
  2844. Board ID = 12
  2845. Set A53 clk to 24M
  2846. Set A73 clk to 24M
  2847. Set clk81 to 24M
  2848. A53 clk: 1200 MHz
  2849. A73 clk: 1200 MHz
  2850. CLK81: 166.6M
  2851. smccc: 00019c3a
  2852. eMMC boot @ 1
  2853. sw8 s
  2854. board id: 12
  2855. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  2856. Get wrong ddr fw magic! Error!!
  2857. fw parse done
  2858. PIEI prepare done
  2859. 00000000
  2860. emmc switch 2 ok
  2861. 00000000
  2862. emmc switch 0 ok
  2863. NO find ddr boot_info from eMMC
  2864. fastboot data verify
  2865. result: 255
  2866. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  2867. LPDDR4 probe
  2868.  
  2869. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  2870. ddr clk to 1608MHz
  2871. 00000000
  2872. emmc switch 1 ok
  2873.  
  2874. dmc_version 0001
  2875. Check phy result
  2876. INFO : End of CA training
  2877. INFO : End of initialization
  2878. INFO : Training has run successfully!
  2879. Check phy result
  2880. INFO : End of initialization
  2881. INFO : End of read enable training
  2882. INFO : End of fine write leveling
  2883. INFO : End of read dq deskew training
  2884. INFO : End of MPR read delay center optimization
  2885. INFO : End of Write leveling coarse delay
  2886. INFO : End of read delay center optimization
  2887. INFO : Training has run successfully!
  2888. Check phy result
  2889. INFO : End of initialization
  2890. INFO : End of MPR read delay center optimization
  2891. INFO : End of write delay center optimization
  2892. INFO : End of read delay center optimization
  2893. INFO : End of max read latency training
  2894. INFO : Training has run successfully!
  2895. 1D training succeed
  2896. Check phy result
  2897. INFO : End of initialization
  2898. INFO : End of 2D read delay Voltage center optimization
  2899. INFO : End of 2D read delay Voltage center optimization
  2900. INFO : End of 2D write delay Voltage center optimization
  2901. INFO : End of 2D write delay Voltage center optimization
  2902. INFO : Training has run successfully!
  2903.  
  2904. soc_vref_reg_value 0x 0000001b 0000001b 0000001d 0000001c 0000001c 0000001a 0000001d 00000017 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001c 0000001b 0000001c 0000001c 0000001c 0000001c 0000001b 0000001b 0000001d 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  2905. dram_vref_reg_value 0x 0000004d
  2906. 2D training succeed
  2907. auto size-- 65535DDR cs0 size: 2048MB
  2908. DDR cs1 size: 2048MB
  2909. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  2910. cs0 DataBus test pass
  2911. cs1 DataBus test pass
  2912. cs0 AddrBus test pass
  2913. cs1 AddrBus test pass
  2914.  
  2915. non-sec scramble use zero key
  2916. ddr scramble enabled
  2917.  
  2918. 100bdlr_step_size ps== 420
  2919. result report
  2920. boot times 0Enable ddr reg access
  2921. 00000000
  2922. emmc switch 3 ok
  2923. Authentication key not yet programmed
  2924. get rpmb counter error 0x00000007
  2925. 00000000
  2926. emmc switch 1 ok
  2927. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  2928. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  2929. BL33 CHK: 0x000000ff ADDR 017a4000
  2930. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  2931. 00000000
  2932. emmc switch 2 ok
  2933. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2934. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  2935. 00000000
  2936. emmc switch 0 ok
  2937. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  2938. reset...
  2939. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  2940. bl2_stage_init 0x01
  2941. bl2_stage_init 0x81
  2942. hw id: 0x0000 - pwm id 0x01
  2943. bl2_stage_init 0xc1
  2944. bl2_stage_init 0x02
  2945.  
  2946. L0:00000000
  2947. L1:20000703
  2948. L2:00008067
  2949. L3:14000000
  2950. B2:00402000
  2951. B1:e0f83180
  2952.  
  2953. TE: 86871
  2954.  
  2955. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  2956.  
  2957. Board ID = 12
  2958. Set A53 clk to 24M
  2959. Set A73 clk to 24M
  2960. Set clk81 to 24M
  2961. A53 clk: 1200 MHz
  2962. A73 clk: 1200 MHz
  2963. CLK81: 166.6M
  2964. smccc: 00019c3a
  2965. eMMC boot @ 1
  2966. sw8 s
  2967. board id: 12
  2968. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  2969. Get wrong ddr fw magic! Error!!
  2970. fw parse done
  2971. PIEI prepare done
  2972. 00000000
  2973. emmc switch 2 ok
  2974. 00000000
  2975. emmc switch 0 ok
  2976. NO find ddr boot_info from eMMC
  2977. fastboot data verify
  2978. result: 255
  2979. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  2980. LPDDR4 probe
  2981.  
  2982. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  2983. ddr clk to 1608MHz
  2984. 00000000
  2985. emmc switch 1 ok
  2986.  
  2987. dmc_version 0001
  2988. Check phy result
  2989. INFO : End of CA training
  2990. INFO : End of initialization
  2991. INFO : Training has run successfully!
  2992. Check phy result
  2993. INFO : End of initialization
  2994. INFO : End of read enable training
  2995. INFO : End of fine write leveling
  2996. INFO : End of read dq deskew training
  2997. INFO : End of MPR read delay center optimization
  2998. INFO : End of Write leveling coarse delay
  2999. INFO : End of read delay center optimization
  3000. INFO : Training has run successfully!
  3001. Check phy result
  3002. INFO : End of initialization
  3003. INFO : End of MPR read delay center optimization
  3004. INFO : End of write delay center optimization
  3005. INFO : End of read delay center optimization
  3006. INFO : End of max read latency training
  3007. INFO : Training has run successfully!
  3008. 1D training succeed
  3009. Check phy result
  3010. INFO : End of initialization
  3011. INFO : End of 2D read delay Voltage center optimization
  3012. INFO : End of 2D read delay Voltage center optimization
  3013. INFO : End of 2D write delay Voltage center optimization
  3014. INFO : End of 2D write delay Voltage center optimization
  3015. INFO : Training has run successfully!
  3016.  
  3017. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001b 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 0000001a 0000001a 0000001c 0000001a 0000001b 0000001b 0000001c 0000001b 0000001c 0000001c 0000001c 0000001c 0000001b 0000001a 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  3018. dram_vref_reg_value 0x 0000004d
  3019. 2D training succeed
  3020. auto size-- 65535DDR cs0 size: 2048MB
  3021. DDR cs1 size: 2048MB
  3022. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  3023. cs0 DataBus test pass
  3024. cs1 DataBus test pass
  3025. cs0 AddrBus test pass
  3026. cs1 AddrBus test pass
  3027.  
  3028. non-sec scramble use zero key
  3029. ddr scramble enabled
  3030.  
  3031. 100bdlr_step_size ps== 425
  3032. result report
  3033. boot times 0Enable ddr reg access
  3034. 00000000
  3035. emmc switch 3 ok
  3036. Authentication key not yet programmed
  3037. get rpmb counter error 0x00000007
  3038. 00000000
  3039. emmc switch 1 ok
  3040. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  3041. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  3042. BL33 CHK: 0x000000ff ADDR 017a4000
  3043. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  3044. 00000000
  3045. emmc switch 2 ok
  3046. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3047. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  3048. 00000000
  3049. emmc switch 0 ok
  3050. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3051. reset...
  3052. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  3053. bl2_stage_init 0x01
  3054. bl2_stage_init 0x81
  3055. hw id: 0x0000 - pwm id 0x01
  3056. bl2_stage_init 0xc1
  3057. bl2_stage_init 0x02
  3058.  
  3059. L0:00000000
  3060. L1:20000703
  3061. L2:00008067
  3062. L3:14000000
  3063. B2:00402000
  3064. B1:e0f83180
  3065.  
  3066. TE: 87018
  3067.  
  3068. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  3069.  
  3070. Board ID = 12
  3071. Set A53 clk to 24M
  3072. Set A73 clk to 24M
  3073. Set clk81 to 24M
  3074. A53 clk: 1200 MHz
  3075. A73 clk: 1200 MHz
  3076. CLK81: 166.6M
  3077. smccc: 00019ccd
  3078. eMMC boot @ 1
  3079. sw8 s
  3080. board id: 12
  3081. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  3082. Get wrong ddr fw magic! Error!!
  3083. fw parse done
  3084. PIEI prepare done
  3085. 00000000
  3086. emmc switch 2 ok
  3087. 00000000
  3088. emmc switch 0 ok
  3089. NO find ddr boot_info from eMMC
  3090. fastboot data verify
  3091. result: 255
  3092. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  3093. LPDDR4 probe
  3094.  
  3095. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  3096. ddr clk to 1608MHz
  3097. 00000000
  3098. emmc switch 1 ok
  3099.  
  3100. dmc_version 0001
  3101. Check phy result
  3102. INFO : End of CA training
  3103. INFO : End of initialization
  3104. INFO : Training has run successfully!
  3105. Check phy result
  3106. INFO : End of initialization
  3107. INFO : End of read enable training
  3108. INFO : End of fine write leveling
  3109. INFO : End of read dq deskew training
  3110. INFO : End of MPR read delay center optimization
  3111. INFO : End of Write leveling coarse delay
  3112. INFO : End of read delay center optimization
  3113. INFO : Training has run successfully!
  3114. Check phy result
  3115. INFO : End of initialization
  3116. INFO : End of MPR read delay center optimization
  3117. INFO : End of write delay center optimization
  3118. INFO : End of read delay center optimization
  3119. INFO : End of max read latency training
  3120. INFO : Training has run successfully!
  3121. 1D training succeed
  3122. Check phy result
  3123. INFO : End of initialization
  3124. INFO : End of 2D read delay Voltage center optimization
  3125. INFO : End of 2D read delay Voltage center optimization
  3126. INFO : End of 2D write delay Voltage center optimization
  3127. INFO : End of 2D write delay Voltage center optimization
  3128. INFO : Training has run successfully!
  3129.  
  3130. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001d 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001d 0000001b 0000001c 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c 0000001c 0000001c 0000001b 0000001d 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  3131. dram_vref_reg_value 0x 0000004d
  3132. 2D training succeed
  3133. auto size-- 65535DDR cs0 size: 2048MB
  3134. DDR cs1 size: 2048MB
  3135. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  3136. cs0 DataBus test pass
  3137. cs1 DataBus test pass
  3138. cs0 AddrBus test pass
  3139. cs1 AddrBus test pass
  3140.  
  3141. non-sec scramble use zero key
  3142. ddr scramble enabled
  3143.  
  3144. 100bdlr_step_size ps== 420
  3145. result report
  3146. boot times 0Enable ddr reg access
  3147. 00000000
  3148. emmc switch 3 ok
  3149. Authentication key not yet programmed
  3150. get rpmb counter error 0x00000007
  3151. 00000000
  3152. emmc switch 1 ok
  3153. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  3154. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  3155. BL33 CHK: 0x000000ff ADDR 017a4000
  3156. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  3157. 00000000
  3158. emmc switch 2 ok
  3159. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3160. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  3161. 00000000
  3162. emmc switch 0 ok
  3163. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3164. reset...
  3165. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  3166. bl2_stage_init 0x01
  3167. bl2_stage_init 0x81
  3168. hw id: 0x0000 - pwm id 0x01
  3169. bl2_stage_init 0xc1
  3170. bl2_stage_init 0x02
  3171.  
  3172. L0:00000000
  3173. L1:20000703
  3174. L2:00008067
  3175. L3:14000000
  3176. B2:00402000
  3177. B1:e0f83180
  3178.  
  3179. TE: 86871
  3180.  
  3181. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  3182.  
  3183. Board ID = 12
  3184. Set A53 clk to 24M
  3185. Set A73 clk to 24M
  3186. Set clk81 to 24M
  3187. A53 clk: 1200 MHz
  3188. A73 clk: 1200 MHz
  3189. CLK81: 166.6M
  3190. smccc: 00019c3a
  3191. eMMC boot @ 1
  3192. sw8 s
  3193. board id: 12
  3194. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  3195. Get wrong ddr fw magic! Error!!
  3196. fw parse done
  3197. PIEI prepare done
  3198. 00000000
  3199. emmc switch 2 ok
  3200. 00000000
  3201. emmc switch 0 ok
  3202. NO find ddr boot_info from eMMC
  3203. fastboot data verify
  3204. result: 255
  3205. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  3206. LPDDR4 probe
  3207.  
  3208. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  3209. ddr clk to 1608MHz
  3210. 00000000
  3211. emmc switch 1 ok
  3212.  
  3213. dmc_version 0001
  3214. Check phy result
  3215. INFO : End of CA training
  3216. INFO : End of initialization
  3217. INFO : Training has run successfully!
  3218. Check phy result
  3219. INFO : End of initialization
  3220. INFO : End of read enable training
  3221. INFO : End of fine write leveling
  3222. INFO : End of read dq deskew training
  3223. INFO : End of MPR read delay center optimization
  3224. INFO : End of Write leveling coarse delay
  3225. INFO : End of read delay center optimization
  3226. INFO : Training has run successfully!
  3227. Check phy result
  3228. INFO : End of initialization
  3229. INFO : End of MPR read delay center optimization
  3230. INFO : End of write delay center optimization
  3231. INFO : End of read delay center optimization
  3232. INFO : End of max read latency training
  3233. INFO : Training has run successfully!
  3234. 1D training succeed
  3235. Check phy result
  3236. INFO : End of initialization
  3237. INFO : End of 2D read delay Voltage center optimization
  3238. INFO : End of 2D read delay Voltage center optimization
  3239. INFO : End of 2D write delay Voltage center optimization
  3240. INFO : End of 2D write delay Voltage center optimization
  3241. INFO : Training has run successfully!
  3242.  
  3243. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001a 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c 0000001c 0000001b 0000001b 0000001e 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  3244. dram_vref_reg_value 0x 0000004d
  3245. 2D training succeed
  3246. auto size-- 65535DDR cs0 size: 2048MB
  3247. DDR cs1 size: 2048MB
  3248. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  3249. cs0 DataBus test pass
  3250. cs1 DataBus test pass
  3251. cs0 AddrBus test pass
  3252. cs1 AddrBus test pass
  3253.  
  3254. non-sec scramble use zero key
  3255. ddr scramble enabled
  3256.  
  3257. 100bdlr_step_size ps== 420
  3258. result report
  3259. boot times 0Enable ddr reg access
  3260. 00000000
  3261. emmc switch 3 ok
  3262. Authentication key not yet programmed
  3263. get rpmb counter error 0x00000007
  3264. 00000000
  3265. emmc switch 1 ok
  3266. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  3267. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  3268. BL33 CHK: 0x000000ff ADDR 017a4000
  3269. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  3270. 00000000
  3271. emmc switch 2 ok
  3272. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3273. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  3274. 00000000
  3275. emmc switch 0 ok
  3276. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3277. reset...
  3278. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  3279. bl2_stage_init 0x01
  3280. bl2_stage_init 0x81
  3281. hw id: 0x0000 - pwm id 0x01
  3282. bl2_stage_init 0xc1
  3283. bl2_stage_init 0x02
  3284.  
  3285. L0:00000000
  3286. L1:20000703
  3287. L2:00008067
  3288. L3:14000000
  3289. B2:00402000
  3290. B1:e0f83180
  3291.  
  3292. TE: 87052
  3293.  
  3294. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  3295.  
  3296. Board ID = 12
  3297. Set A53 clk to 24M
  3298. Set A73 clk to 24M
  3299. Set clk81 to 24M
  3300. A53 clk: 1200 MHz
  3301. A73 clk: 1200 MHz
  3302. CLK81: 166.6M
  3303. smccc: 00019cf1
  3304. eMMC boot @ 1
  3305. sw8 s
  3306. board id: 12
  3307. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  3308. Get wrong ddr fw magic! Error!!
  3309. fw parse done
  3310. PIEI prepare done
  3311. 00000000
  3312. emmc switch 2 ok
  3313. 00000000
  3314. emmc switch 0 ok
  3315. NO find ddr boot_info from eMMC
  3316. fastboot data verify
  3317. result: 255
  3318. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  3319. LPDDR4 probe
  3320.  
  3321. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  3322. ddr clk to 1608MHz
  3323. 00000000
  3324. emmc switch 1 ok
  3325.  
  3326. dmc_version 0001
  3327. Check phy result
  3328. INFO : End of CA training
  3329. INFO : End of initialization
  3330. INFO : Training has run successfully!
  3331. Check phy result
  3332. INFO : End of initialization
  3333. INFO : End of read enable training
  3334. INFO : End of fine write leveling
  3335. INFO : End of read dq deskew training
  3336. INFO : End of MPR read delay center optimization
  3337. INFO : End of Write leveling coarse delay
  3338. INFO : End of read delay center optimization
  3339. INFO : Training has run successfully!
  3340. Check phy result
  3341. INFO : End of initialization
  3342. INFO : End of MPR read delay center optimization
  3343. INFO : End of write delay center optimization
  3344. INFO : End of read delay center optimization
  3345. INFO : End of max read latency training
  3346. INFO : Training has run successfully!
  3347. 1D training succeed
  3348. Check phy result
  3349. INFO : End of initialization
  3350. INFO : End of 2D read delay Voltage center optimization
  3351. INFO : End of 2D read delay Voltage center optimization
  3352. INFO : End of 2D write delay Voltage center optimization
  3353. INFO : End of 2D write delay Voltage center optimization
  3354. INFO : Training has run successfully!
  3355.  
  3356. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001d 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001d 0000001b 0000001c 0000001c 0000001b 0000001a 0000001b 0000001c 0000001b 0000001c 0000001b 0000001a 0000001d 0000001a 0000001b 0000001b 0000001a 0000001b 0000001c 0000001b dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  3357. dram_vref_reg_value 0x 0000004e
  3358. 2D training succeed
  3359. auto size-- 65535DDR cs0 size: 2048MB
  3360. DDR cs1 size: 2048MB
  3361. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  3362. cs0 DataBus test pass
  3363. cs1 DataBus test pass
  3364. cs0 AddrBus test pass
  3365. cs1 AddrBus test pass
  3366.  
  3367. non-sec scramble use zero key
  3368. ddr scramble enabled
  3369.  
  3370. 100bdlr_step_size ps== 420
  3371. result report
  3372. boot times 0Enable ddr reg access
  3373. 00000000
  3374. emmc switch 3 ok
  3375. Authentication key not yet programmed
  3376. get rpmb counter error 0x00000007
  3377. 00000000
  3378. emmc switch 1 ok
  3379. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  3380. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  3381. BL33 CHK: 0x000000ff ADDR 017a4000
  3382. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  3383. 00000000
  3384. emmc switch 2 ok
  3385. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3386. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  3387. 00000000
  3388. emmc switch 0 ok
  3389. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3390. reset...
  3391. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  3392. bl2_stage_init 0x01
  3393. bl2_stage_init 0x81
  3394. hw id: 0x0000 - pwm id 0x01
  3395. bl2_stage_init 0xc1
  3396. bl2_stage_init 0x02
  3397.  
  3398. L0:00000000
  3399. L1:20000703
  3400. L2:00008067
  3401. L3:14000000
  3402. B2:00402000
  3403. B1:e0f83180
  3404.  
  3405. TE: 86870
  3406.  
  3407. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  3408.  
  3409. Board ID = 12
  3410. Set A53 clk to 24M
  3411. Set A73 clk to 24M
  3412. Set clk81 to 24M
  3413. A53 clk: 1200 MHz
  3414. A73 clk: 1200 MHz
  3415. CLK81: 166.6M
  3416. smccc: 00019c3a
  3417. eMMC boot @ 1
  3418. sw8 s
  3419. board id: 12
  3420. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  3421. Get wrong ddr fw magic! Error!!
  3422. fw parse done
  3423. PIEI prepare done
  3424. 00000000
  3425. emmc switch 2 ok
  3426. 00000000
  3427. emmc switch 0 ok
  3428. NO find ddr boot_info from eMMC
  3429. fastboot data verify
  3430. result: 255
  3431. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  3432. LPDDR4 probe
  3433.  
  3434. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  3435. ddr clk to 1608MHz
  3436. 00000000
  3437. emmc switch 1 ok
  3438.  
  3439. dmc_version 0001
  3440. Check phy result
  3441. INFO : End of CA training
  3442. INFO : End of initialization
  3443. INFO : Training has run successfully!
  3444. Check phy result
  3445. INFO : End of initialization
  3446. INFO : End of read enable training
  3447. INFO : End of fine write leveling
  3448. INFO : End of read dq deskew training
  3449. INFO : End of MPR read delay center optimization
  3450. INFO : End of Write leveling coarse delay
  3451. INFO : End of read delay center optimization
  3452. INFO : Training has run successfully!
  3453. Check phy result
  3454. INFO : End of initialization
  3455. INFO : End of MPR read delay center optimization
  3456. INFO : End of write delay center optimization
  3457. INFO : End of read delay center optimization
  3458. INFO : End of max read latency training
  3459. INFO : Training has run successfully!
  3460. 1D training succeed
  3461. Check phy result
  3462. INFO : End of initialization
  3463. INFO : End of 2D read delay Voltage center optimization
  3464. INFO : End of 2D read delay Voltage center optimization
  3465. INFO : End of 2D write delay Voltage center optimization
  3466. INFO : End of 2D write delay Voltage center optimization
  3467. INFO : Training has run successfully!
  3468.  
  3469. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001d 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001d 0000001b 0000001c 0000001c 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001a 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  3470. dram_vref_reg_value 0x 0000004d
  3471. 2D training succeed
  3472. auto size-- 65535DDR cs0 size: 2048MB
  3473. DDR cs1 size: 2048MB
  3474. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  3475. cs0 DataBus test pass
  3476. cs1 DataBus test pass
  3477. cs0 AddrBus test pass
  3478. cs1 AddrBus test pass
  3479.  
  3480. non-sec scramble use zero key
  3481. ddr scramble enabled
  3482.  
  3483. 100bdlr_step_size ps== 420
  3484. result report
  3485. boot times 0Enable ddr reg access
  3486. 00000000
  3487. emmc switch 3 ok
  3488. Authentication key not yet programmed
  3489. get rpmb counter error 0x00000007
  3490. 00000000
  3491. emmc switch 1 ok
  3492. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  3493. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  3494. BL33 CHK: 0x000000ff ADDR 017a4000
  3495. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  3496. 00000000
  3497. emmc switch 2 ok
  3498. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3499. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  3500. 00000000
  3501. emmc switch 0 ok
  3502. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3503. reset...
  3504. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  3505. bl2_stage_init 0x01
  3506. bl2_stage_init 0x81
  3507. hw id: 0x0000 - pwm id 0x01
  3508. bl2_stage_init 0xc1
  3509. bl2_stage_init 0x02
  3510.  
  3511. L0:00000000
  3512. L1:20000703
  3513. L2:00008067
  3514. L3:14000000
  3515. B2:00402000
  3516. B1:e0f83180
  3517.  
  3518. TE: 87027
  3519.  
  3520. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  3521.  
  3522. Board ID = 12
  3523. Set A53 clk to 24M
  3524. Set A73 clk to 24M
  3525. Set clk81 to 24M
  3526. A53 clk: 1200 MHz
  3527. A73 clk: 1200 MHz
  3528. CLK81: 166.6M
  3529. smccc: 00019cd6
  3530. eMMC boot @ 1
  3531. sw8 s
  3532. board id: 12
  3533. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  3534. Get wrong ddr fw magic! Error!!
  3535. fw parse done
  3536. PIEI prepare done
  3537. 00000000
  3538. emmc switch 2 ok
  3539. 00000000
  3540. emmc switch 0 ok
  3541. NO find ddr boot_info from eMMC
  3542. fastboot data verify
  3543. result: 255
  3544. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  3545. LPDDR4 probe
  3546.  
  3547. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  3548. ddr clk to 1608MHz
  3549. 00000000
  3550. emmc switch 1 ok
  3551.  
  3552. dmc_version 0001
  3553. Check phy result
  3554. INFO : End of CA training
  3555. INFO : End of initialization
  3556. INFO : Training has run successfully!
  3557. Check phy result
  3558. INFO : End of initialization
  3559. INFO : End of read enable training
  3560. INFO : End of fine write leveling
  3561. INFO : End of read dq deskew training
  3562. INFO : End of MPR read delay center optimization
  3563. INFO : End of Write leveling coarse delay
  3564. INFO : End of read delay center optimization
  3565. INFO : Training has run successfully!
  3566. Check phy result
  3567. INFO : End of initialization
  3568. INFO : End of MPR read delay center optimization
  3569. INFO : End of write delay center optimization
  3570. INFO : End of read delay center optimization
  3571. INFO : End of max read latency training
  3572. INFO : Training has run successfully!
  3573. 1D training succeed
  3574. Check phy result
  3575. INFO : End of initialization
  3576. INFO : End of 2D read delay Voltage center optimization
  3577. INFO : End of 2D read delay Voltage center optimization
  3578. INFO : End of 2D write delay Voltage center optimization
  3579. INFO : End of 2D write delay Voltage center optimization
  3580. INFO : Training has run successfully!
  3581.  
  3582. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001c 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 0000001a 0000001a 0000001c 0000001a 0000001b 0000001b 0000001b 0000001a 0000001b 0000001c 0000001b 0000001b 0000001b 0000001a 0000001c 0000001a 0000001b 0000001b 0000001a 0000001b 0000001c 0000001b dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  3583. dram_vref_reg_value 0x 0000004e
  3584. 2D training succeed
  3585. auto size-- 65535DDR cs0 size: 2048MB
  3586. DDR cs1 size: 2048MB
  3587. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  3588. cs0 DataBus test pass
  3589. cs1 DataBus test pass
  3590. cs0 AddrBus test pass
  3591. cs1 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  3592. bl2_stage_init 0x01
  3593. bl2_stage_init 0x81
  3594. hw id: 0x0000 - pwm id 0x01
  3595. bl2_stage_init 0xc1
  3596. bl2_stage_init 0x02
  3597.  
  3598. L0:00000000
  3599. L1:20000703
  3600. L2:00008067
  3601. L3:14000000
  3602. B2:00402000
  3603. B1:e0f83180
  3604.  
  3605. TE: 195265
  3606.  
  3607. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  3608.  
  3609. Board ID = 12
  3610. Set A53 clk to 24M
  3611. Set A73 clk to 24M
  3612. Set clk81 to 24M
  3613. A53 clk: 1200 MHz
  3614. A73 clk: 1200 MHz
  3615. CLK81: 166.6M
  3616. smccc: 000343fc
  3617. eMMC boot @ 1
  3618. sw8 s
  3619. board id: 12
  3620. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  3621. Get wrong ddr fw magic! Error!!
  3622. fw parse done
  3623. PIEI prepare done
  3624. 00000000
  3625. emmc switch 2 ok
  3626. 00000000
  3627. emmc switch 0 ok
  3628. NO find ddr boot_info from eMMC
  3629. fastboot data verify
  3630. result: 255
  3631. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  3632. LPDDR4 probe
  3633.  
  3634. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  3635. ddr clk to 1608MHz
  3636. 00000000
  3637. emmc switch 1 ok
  3638.  
  3639. dmc_version 0001
  3640. Check phy result
  3641. INFO : End of CA training
  3642. INFO : End of initialization
  3643. INFO : Training has run successfully!
  3644. Check phy result
  3645. INFO : End of initialization
  3646. INFO : End of read enable training
  3647. INFO : End of fine write leveling
  3648. INFO : End of read dq deskew training
  3649. INFO : End of MPR read delay center optimization
  3650. INFO : End of Write leveling coarse delay
  3651. INFO : End of read delay center optimization
  3652. INFO : Training has run successfully!
  3653. Check phy result
  3654. INFO : End of initialization
  3655. INFO : End of MPR read delay center optimization
  3656. INFO : End of write delay center optimization
  3657. INFO : End of read delay center optimization
  3658. INFO : End of max read latency training
  3659. INFO : Training has run successfully!
  3660. 1D training succeed
  3661. Check phy result
  3662. INFO : End of initialization
  3663. INFO : End of 2D read delay Voltage center optimization
  3664. INFO : End of 2D read delay Voltage center optimization
  3665. INFO : End of 2D write delay Voltage center optimization
  3666. INFO : End of 2D write delay Voltage center optimization
  3667. INFO : Training has run successfully!
  3668.  
  3669. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001a 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001c 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001b 0000001d 0000001b 0000001b 0000001c 0000001b 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  3670. dram_vref_reg_value 0x 0000004d
  3671. 2D training succeed
  3672. auto size-- 65535DDR cs0 size: 2048MB
  3673. DDR cs1 size: 2048MB
  3674. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  3675. cs0 DataBus test pass
  3676. cs1 DataBus test pass
  3677. cs0 AddrBus test pass
  3678. cs1 AddrBus test pass
  3679.  
  3680. non-sec scramble use zero key
  3681. ddr scramble enabled
  3682.  
  3683. 100bdlr_step_size ps== 425
  3684. result report
  3685. boot times 0Enable ddr reg access
  3686. 00000000
  3687. emmc switch 3 ok
  3688. Authentication key not yet programmed
  3689. get rpmb counter error 0x00000007
  3690. 00000000
  3691. emmc switch 1 ok
  3692. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  3693. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  3694. BL33 CHK: 0x000000ff ADDR 017a4000
  3695. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  3696. 00000000
  3697. emmc switch 2 ok
  3698. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3699. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  3700. 00000000
  3701. emmc switch 0 ok
  3702. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3703. reset...
  3704. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  3705. bl2_stage_init 0x01
  3706. bl2_stage_init 0x81
  3707. hw id: 0x0000 - pwm id 0x01
  3708. bl2_stage_init 0xc1
  3709. bl2_stage_init 0x02
  3710.  
  3711. L0:00000000
  3712. L1:20000703
  3713. L2:00008067
  3714. L3:14000000
  3715. B2:00402000
  3716. B1:e0f83180
  3717.  
  3718. TE: 87165
  3719.  
  3720. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  3721.  
  3722. Board ID = 12
  3723. Set A53 clk to 24M
  3724. Set A73 clk to 24M
  3725. Set clk81 to 24M
  3726. A53 clk: 1200 MHz
  3727. A73 clk: 1200 MHz
  3728. CLK81: 166.6M
  3729. smccc: 00019d61
  3730. eMMC boot @ 1
  3731. sw8 s
  3732. board id: 12
  3733. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  3734. Get wrong ddr fw magic! Error!!
  3735. fw parse done
  3736. PIEI prepare done
  3737. 00000000
  3738. emmc switch 2 ok
  3739. 00000000
  3740. emmc switch 0 ok
  3741. NO find ddr boot_info from eMMC
  3742. fastboot data verify
  3743. result: 255
  3744. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  3745. LPDDR4 probe
  3746.  
  3747. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  3748. ddr clk to 1608MHz
  3749. 00000000
  3750. emmc switch 1 ok
  3751.  
  3752. dmc_version 0001
  3753. Check phy result
  3754. INFO : End of CA training
  3755. INFO : End of initialization
  3756. INFO : Training has run successfully!
  3757. Check phy result
  3758. INFO : End of initialization
  3759. INFO : End of read enable training
  3760. INFO : End of fine write leveling
  3761. INFO : End of read dq deskew training
  3762. INFO : End of MPR read delay center optimization
  3763. INFO : End of Write leveling coarse delay
  3764. INFO : End of read delay center optimization
  3765. INFO : Training has run successfully!
  3766. Check phy result
  3767. INFO : End of initialization
  3768. INFO : End of MPR read delay center optimization
  3769. INFO : End of write delay center optimization
  3770. INFO : End of read delay center optimization
  3771. INFO : End of max read latency training
  3772. INFO : Training has run successfully!
  3773. 1D training succeed
  3774. Check phy result
  3775. INFO : End of initialization
  3776. INFO : End of 2D read delay Voltage center optimization
  3777. INFO : End of 2D read delay Voltage center optimization
  3778. INFO : End of 2D write delay Voltage center optimization
  3779. INFO : End of 2D write delay Voltage center optimization
  3780. INFO : Training has run successfully!
  3781.  
  3782. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001c 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 0000001a 00000019 0000001c 0000001a 0000001b 0000001b 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001a 0000001d 0000001a 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  3783. dram_vref_reg_value 0x 0000004d
  3784. 2D training succeed
  3785. auto size-- 65535DDR cs0 size: 2048MB
  3786. DDR cs1 size: 2048MB
  3787. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  3788. cs0 DataBus test pass
  3789. cs1 DataBus test pass
  3790. cs0 AddrBus test pass
  3791. cs1 AddrBus test pass
  3792.  
  3793. non-sec scramble use zero key
  3794. ddr scramble enabled
  3795.  
  3796. 100bdlr_step_size ps== 425
  3797. result report
  3798. boot times 0Enable ddr reg access
  3799. 00000000
  3800. emmc switch 3 ok
  3801. Authentication key not yet programmed
  3802. get rpmb counter error 0x00000007
  3803. 00000000
  3804. emmc switch 1 ok
  3805. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  3806. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  3807. BL33 CHK: 0x000000ff ADDR 017a4000
  3808. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  3809. 00000000
  3810. emmc switch 2 ok
  3811. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3812. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  3813. 00000000
  3814. emmc switch 0 ok
  3815. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3816. reset...
  3817. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  3818. bl2_stage_init 0x01
  3819. bl2_stage_init 0x81
  3820. hw id: 0x0000 - pwm id 0x01
  3821. bl2_stage_init 0xc1
  3822. bl2_stage_init 0x02
  3823.  
  3824. L0:00000000
  3825. L1:20000703
  3826. L2:00008067
  3827. L3:14000000
  3828. B2:00402000
  3829. B1:e0f83180
  3830.  
  3831. TE: 87044
  3832.  
  3833. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  3834.  
  3835. Board ID = 12
  3836. Set A53 clk to 24M
  3837. Set A73 clk to 24M
  3838. Set clk81 to 24M
  3839. A53 clk: 1200 MHz
  3840. A73 clk: 1200 MHz
  3841. CLK81: 166.6M
  3842. smccc: 00019ce8
  3843. eMMC boot @ 1
  3844. sw8 s
  3845. board id: 12
  3846. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  3847. Get wrong ddr fw magic! Error!!
  3848. fw parse done
  3849. PIEI prepare done
  3850. 00000000
  3851. emmc switch 2 ok
  3852. 00000000
  3853. emmc switch 0 ok
  3854. NO find ddr boot_info from eMMC
  3855. fastboot data verify
  3856. result: 255
  3857. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  3858. LPDDR4 probe
  3859.  
  3860. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  3861. ddr clk to 1608MHz
  3862. 00000000
  3863. emmc switch 1 ok
  3864.  
  3865. dmc_version 0001
  3866. Check phy result
  3867. INFO : End of CA training
  3868. INFO : End of initialization
  3869. INFO : Training has run successfully!
  3870. Check phy result
  3871. INFO : End of initialization
  3872. INFO : End of read enable training
  3873. INFO : End of fine write leveling
  3874. INFO : End of read dq deskew training
  3875. INFO : End of MPR read delay center optimization
  3876. INFO : End of Write leveling coarse delay
  3877. INFO : End of read delay center optimization
  3878. INFO : Training has run successfully!
  3879. Check phy result
  3880. INFO : End of initialization
  3881. INFO : End of MPR read delay center optimization
  3882. INFO : End of write delay center optimization
  3883. INFO : End of read delay center optimization
  3884. INFO : End of max read latency training
  3885. INFO : Training has run successfully!
  3886. 1D training succeed
  3887. Check phy result
  3888. INFO : End of initialization
  3889. INFO : End of 2D read delay Voltage center optimization
  3890. INFO : End of 2D read delay Voltage center optimization
  3891. INFO : End of 2D write delay Voltage center optimization
  3892. INFO : End of 2D write delay Voltage center optimization
  3893. INFO : Training has run successfully!
  3894.  
  3895. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001d 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001d 0000001b 0000001b 0000001c 0000001c 0000001b 0000001c 0000001c 0000001c 0000001d 0000001c 0000001b 0000001d 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  3896. dram_vref_reg_value 0x 0000004d
  3897. 2D training succeed
  3898. auto size-- 65535DDR cs0 size: 2048MB
  3899. DDR cs1 size: 2048MB
  3900. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  3901. cs0 DataBus test pass
  3902. cs1 DataBus test pass
  3903. cs0 AddrBus test pass
  3904. cs1 AddrBus test pass
  3905.  
  3906. non-sec scramble use zero key
  3907. ddr scramble enabled
  3908.  
  3909. 100bdlr_step_size ps== 420
  3910. result report
  3911. boot times 0Enable ddr reg access
  3912. 00000000
  3913. emmc switch 3 ok
  3914. Authentication key not yet programmed
  3915. get rpmb counter error 0x00000007
  3916. 00000000
  3917. emmc switch 1 ok
  3918. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  3919. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  3920. BL33 CHK: 0x000000ff ADDR 017a4000
  3921. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  3922. 00000000
  3923. emmc switch 2 ok
  3924. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3925. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  3926. 00000000
  3927. emmc switch 0 ok
  3928. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  3929. reset...
  3930. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  3931. bl2_stage_init 0x01
  3932. bl2_stage_init 0x81
  3933. hw id: 0x0000 - pwm id 0x01
  3934. bl2_stage_init 0xc1
  3935. bl2_stage_init 0x02
  3936.  
  3937. L0:00000000
  3938. L1:20000703
  3939. L2:00008067
  3940. L3:14000000
  3941. B2:00402000
  3942. B1:e0f83180
  3943.  
  3944. TE: 86870
  3945.  
  3946. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  3947.  
  3948. Board ID = 12
  3949. Set A53 clk to 24M
  3950. Set A73 clk to 24M
  3951. Set clk81 to 24M
  3952. A53 clk: 1200 MHz
  3953. A73 clk: 1200 MHz
  3954. CLK81: 166.6M
  3955. smccc: 00019c3a
  3956. eMMC boot @ 1
  3957. sw8 s
  3958. board id: 12
  3959. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  3960. Get wrong ddr fw magic! Error!!
  3961. fw parse done
  3962. PIEI prepare done
  3963. 00000000
  3964. emmc switch 2 ok
  3965. 00000000
  3966. emmc switch 0 ok
  3967. NO find ddr boot_info from eMMC
  3968. fastboot data verify
  3969. result: 255
  3970. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  3971. LPDDR4 probe
  3972.  
  3973. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  3974. ddr clk to 1608MHz
  3975. 00000000
  3976. emmc switch 1 ok
  3977.  
  3978. dmc_version 0001
  3979. Check phy result
  3980. INFO : End of CA training
  3981. INFO : End of initialization
  3982. INFO : Training has run successfully!
  3983. Check phy result
  3984. INFO : End of initialization
  3985. INFO : End of read enable training
  3986. INFO : End of fine write leveling
  3987. INFO : End of read dq deskew training
  3988. INFO : End of MPR read delay center optimization
  3989. INFO : End of Write leveling coarse delay
  3990. INFO : End of read delay center optimization
  3991. INFO : Training has run successfully!
  3992. Check phy result
  3993. INFO : End of initialization
  3994. INFO : End of MPR read delay center optimization
  3995. INFO : End of write delay center optimization
  3996. INFO : End of read delay center optimization
  3997. INFO : End of max read latency training
  3998. INFO : Training has run successfully!
  3999. 1D training succeed
  4000. Check phy result
  4001. INFO : End of initialization
  4002. INFO : End of 2D read delay Voltage center optimization
  4003. INFO : End of 2D read delay Voltage center optimization
  4004. INFO : End of 2D write delay Voltage center optimization
  4005. INFO : End of 2D write delay Voltage center optimization
  4006. INFO : Training has run successfully!
  4007.  
  4008. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001d 0000001b 0000001d 00000018 0000001c 0000001b 0000001b 0000001a 0000001c 0000001b 0000001c 0000001c 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001b 0000001d 0000001b 0000001b 0000001c 0000001b 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  4009. dram_vref_reg_value 0x 0000004d
  4010. 2D training succeed
  4011. auto size-- 65535DDR cs0 size: 2048MB
  4012. DDR cs1 size: 2048MB
  4013. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  4014. cs0 DataBus test pass
  4015. cs1 DataBus test pass
  4016. cs0 AddrBus test pass
  4017. cs1 AddrBus test pass
  4018.  
  4019. non-sec scramble use zero key
  4020. ddr scramble enabled
  4021.  
  4022. 100bdlr_step_size ps== 420
  4023. result report
  4024. boot times 0Enable ddr reg access
  4025. 00000000
  4026. emmc switch 3 ok
  4027. Authentication key not yet programmed
  4028. get rpmb counter error 0x00000007
  4029. 00000000
  4030. emmc switch 1 ok
  4031. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  4032. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  4033. BL33 CHK: 0x000000ff ADDR 017a4000
  4034. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  4035. 00000000
  4036. emmc switch 2 ok
  4037. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  4038. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  4039. 00000000
  4040. emmc switch 0 ok
  4041. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  4042. reset...
  4043. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  4044. bl2_stage_init 0x01
  4045. bl2_stage_init 0x81
  4046. hw id: 0x0000 - pwm id 0x01
  4047. bl2_stage_init 0xc1
  4048. bl2_stage_init 0x02
  4049.  
  4050. L0:00000000
  4051. L1:20000703
  4052. L2:00008067
  4053. L3:14000000
  4054. B2:00402000
  4055. B1:e0f83180
  4056.  
  4057. TE: 87070
  4058.  
  4059. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  4060.  
  4061. Board ID = 12
  4062. Set A53 clk to 24M
  4063. Set A73 clk to 24M
  4064. Set clk81 to 24M
  4065. A53 clk: 1200 MHz
  4066. A73 clk: 1200 MHz
  4067. CLK81: 166.6M
  4068. smccc: 00019d01
  4069. eMMC boot @ 1
  4070. sw8 s
  4071. board id: 12
  4072. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  4073. Get wrong ddr fw magic! Error!!
  4074. fw parse done
  4075. PIEI prepare done
  4076. 00000000
  4077. emmc switch 2 ok
  4078. 00000000
  4079. emmc switch 0 ok
  4080. NO find ddr boot_info from eMMC
  4081. fastboot data verify
  4082. result: 255
  4083. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  4084. LPDDR4 probe
  4085.  
  4086. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  4087. ddr clk to 1608MHz
  4088. 00000000
  4089. emmc switch 1 ok
  4090.  
  4091. dmc_version 0001
  4092. Check phy result
  4093. INFO : End of CA training
  4094. INFO : End of initialization
  4095. INFO : Training has run successfully!
  4096. Check phy result
  4097. INFO : End of initialization
  4098. INFO : End of read enable training
  4099. INFO : End of fine write leveling
  4100. INFO : End of read dq deskew training
  4101. INFO : End of MPR read delay center optimization
  4102. INFO : End of Write leveling coarse delay
  4103. INFO : End of read delay center optimization
  4104. INFO : Training has run successfully!
  4105. Check phy result
  4106. INFO : End of initialization
  4107. INFO : End of MPR read delay center optimization
  4108. INFO : End of write delay center optimization
  4109. INFO : End of read delay center optimization
  4110. INFO : End of max read latency training
  4111. INFO : Training has run successfully!
  4112. 1D training succeed
  4113. Check phy result
  4114. INFO : End of initialization
  4115. INFO : End of 2D read delay Voltage center optimization
  4116. INFO : End of 2D read delay Voltage center optimization
  4117. INFO : End of 2D write delay Voltage center optimization
  4118. INFO : End of 2D write delay Voltage center optimization
  4119. INFO : Training has run successfully!
  4120.  
  4121. soc_vref_reg_value 0x 0000001b 0000001a 0000001c 0000001c 0000001c 0000001a 0000001c 00000017 0000001b 0000001a 0000001a 0000001a 0000001c 0000001a 0000001b 0000001b 0000001c 0000001a 0000001c 0000001c 0000001c 0000001c 0000001b 0000001b 0000001d 0000001b 0000001b 0000001c 0000001a 0000001b 0000001c 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  4122. dram_vref_reg_value 0x 0000004d
  4123. 2D training succeed
  4124. auto size-- 65535DDR cs0 size: 2048MB
  4125. DDR cs1 size: 2048MB
  4126. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  4127. cs0 DataBus test pass
  4128. cs1 DataBus test pass
  4129. cs0 AddrBus test pass
  4130. cs1 AddrBus test pass
  4131.  
  4132. non-sec scramble use zero key
  4133. ddr scramble enabled
  4134.  
  4135. 100bdlr_step_size ps== 420
  4136. result report
  4137. boot times 0Enable ddr reg access
  4138. 00000000
  4139. emmc switch 3 ok
  4140. Authentication key not yet programmed
  4141. get rpmb counter error 0x00000007
  4142. 00000000
  4143. emmc switch 1 ok
  4144. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  4145. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  4146. BL33 CHK: 0x000000ff ADDR 017a4000
  4147. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  4148. 00000000
  4149. emmc switch 2 ok
  4150. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  4151. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  4152. 00000000
  4153. emmc switch 0 ok
  4154. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  4155. reset...
  4156. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  4157. bl2_stage_init 0x01
  4158. bl2_stage_init 0x81
  4159. hw id: 0x0000 - pwm id 0x01
  4160. bl2_stage_init 0xc1
  4161. bl2_stage_init 0x02
  4162.  
  4163. L0:00000000
  4164. L1:20000703
  4165. L2:00008067
  4166. L3:14000000
  4167. B2:00402000
  4168. B1:e0f83180
  4169.  
  4170. TE: 86870
  4171.  
  4172. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  4173.  
  4174. Board ID = 12
  4175. Set A53 clk to 24M
  4176. Set A73 clk to 24M
  4177. Set clk81 to 24M
  4178. A53 clk: 1200 MHz
  4179. A73 clk: 1200 MHz
  4180. CLK81: 166.6M
  4181. smccc: 00019c3a
  4182. eMMC boot @ 1
  4183. sw8 s
  4184. board id: 12
  4185. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  4186. Get wrong ddr fw magic! Error!!
  4187. fw parse done
  4188. PIEI prepare done
  4189. 00000000
  4190. emmc switch 2 ok
  4191. 00000000
  4192. emmc switch 0 ok
  4193. NO find ddr boot_info from eMMC
  4194. fastboot data verify
  4195. result: 255
  4196. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  4197. LPDDR4 probe
  4198.  
  4199. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  4200. ddr clk to 1608MHz
  4201. 00000000
  4202. emmc switch 1 ok
  4203.  
  4204. dmc_version 0001
  4205. Check phy result
  4206. INFO : End of CA training
  4207. INFO : End of initialization
  4208. INFO : Training has run successfully!
  4209. Check phy result
  4210. INFO : End of initialization
  4211. INFO : End of read enable training
  4212. INFO : End of fine write leveling
  4213. INFO : End of read dq deskew training
  4214. INFO : End of MPR read delay center optimization
  4215. INFO : End of Write leveling coarse delay
  4216. INFO : End of read delay center optimization
  4217. INFO : Training has run successfully!
  4218. Check phy result
  4219. INFO : End of initialization
  4220. INFO : End of MPR read delay center optimization
  4221. INFO : End of write delay center optimization
  4222. INFO : End of read delay center optimization
  4223. INFO : End of max read latency training
  4224. INFO : Training has run successfully!
  4225. 1D training succeed
  4226. Check phy result
  4227. INFO : End of initialization
  4228. INFO : End of 2D read delay Voltage center optimization
  4229. INFO : End of 2D read delay Voltage center optimization
  4230. INFO : End of 2D write delay Voltage center optimization
  4231. INFO : End of 2D write delay Voltage center optimization
  4232. INFO : Training has run successfully!
  4233.  
  4234. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001c 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001c 0000001b 0000001b 0000001b 0000001b 0000001a 0000001b 0000001c 0000001b 0000001b 0000001b 0000001a 0000001c 0000001a 0000001b 0000001b 0000001a 0000001b 0000001c 0000001b dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  4235. dram_vref_reg_value 0x 0000004d
  4236. 2D training succeed
  4237. auto size-- 65535DDR cs0 size: 2048MB
  4238. DDR cs1 size: 2048MB
  4239. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  4240. cs0 DataBus test pass
  4241. cs1 DataBus test pass
  4242. cs0 AddrBus test pass
  4243. cs1 AddrBus test pass
  4244.  
  4245. non-sec scramble use zero key
  4246. ddr scramble enabled
  4247.  
  4248. 100bdlr_step_size ps== 420
  4249. result report
  4250. boot times 0Enable ddr reg access
  4251. 00000000
  4252. emmc switch 3 ok
  4253. Authentication key not yet programmed
  4254. get rpmb counter error 0x00000007
  4255. 00000000
  4256. emmc switch 1 ok
  4257. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  4258. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  4259. BL33 CHK: 0x000000ff ADDR 017a4000
  4260. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  4261. 00000000
  4262. emmc switch 2 ok
  4263. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  4264. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  4265. 00000000
  4266. emmc switch 0 ok
  4267. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  4268. reset...
  4269. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  4270. bl2_stage_init 0x01
  4271. bl2_stage_init 0x81
  4272. hw id: 0x0000 - pwm id 0x01
  4273. bl2_stage_init 0xc1
  4274. bl2_stage_init 0x02
  4275.  
  4276. L0:00000000
  4277. L1:20000703
  4278. L2:00008067
  4279. L3:14000000
  4280. B2:00402000
  4281. B1:e0f83180
  4282.  
  4283. TE: 86870
  4284.  
  4285. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  4286.  
  4287. Board ID = 12
  4288. Set A53 clk to 24M
  4289. Set A73 clk to 24M
  4290. Set clk81 to 24M
  4291. A53 clk: 1200 MHz
  4292. A73 clk: 1200 MHz
  4293. CLK81: 166.6M
  4294. smccc: 00019c3a
  4295. eMMC boot @ 1
  4296. sw8 s
  4297. board id: 12
  4298. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  4299. Get wrong ddr fw magic! Error!!
  4300. fw parse done
  4301. PIEI prepare done
  4302. 00000000
  4303. emmc switch 2 ok
  4304. 00000000
  4305. emmc switch 0 ok
  4306. NO find ddr boot_info from eMMC
  4307. fastboot data verify
  4308. result: 255
  4309. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  4310. LPDDR4 probe
  4311.  
  4312. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  4313. ddr clk to 1608MHz
  4314. 00000000
  4315. emmc switch 1 ok
  4316.  
  4317. dmc_version 0001
  4318. Check phy result
  4319. INFO : End of CA training
  4320. INFO : End of initialization
  4321. INFO : Training has run successfully!
  4322. Check phy result
  4323. INFO : End of initialization
  4324. INFO : End of read enable training
  4325. INFO : End of fine write leveling
  4326. INFO : End of read dq deskew training
  4327. INFO : End of MPR read delay center optimization
  4328. INFO : End of Write leveling coarse delay
  4329. INFO : End of read delay center optimization
  4330. INFO : Training has run successfully!
  4331. Check phy result
  4332. INFO : End of initialization
  4333. INFO : End of MPR read delay center optimization
  4334. INFO : End of write delay center optimization
  4335. INFO : End of read delay center optimization
  4336. INFO : End of max read latency training
  4337. INFO : Training has run successfully!
  4338. 1D training succeed
  4339. Check phy result
  4340. INFO : End of initialization
  4341. INFO : End of 2D read delay Voltage center optimization
  4342. INFO : End of 2D read delay Voltage center optimization
  4343. INFO : End of 2D write delay Voltage center optimization
  4344. INFO : End of 2D write delay Voltage center optimization
  4345. INFO : Training has run successfully!
  4346.  
  4347. soc_vref_reg_value 0x 0000001c 0000001b 0000001d 0000001c 0000001d 0000001b 0000001d 00000018 0000001c 0000001b 0000001a 0000001a 0000001d 0000001b 0000001c 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c 0000001d 0000001c 0000001c 0000001e 0000001b 0000001c 0000001c 0000001b 0000001c 0000001d 0000001c dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  4348. dram_vref_reg_value 0x 0000004d
  4349. 2D training succeed
  4350. auto size-- 65535DDR cs0 size: 2048MB
  4351. DDR cs1 size: 2048MB
  4352. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  4353. cs0 DataBus test pass
  4354. cs1 DataBus test pass
  4355. cs0 AddrBus test pass
  4356. cs1 AddrBus test pass
  4357.  
  4358. non-sec scramble use zero key
  4359. ddr scramble enabled
  4360.  
  4361. 100bdlr_step_size ps== 431
  4362. result report
  4363. boot times 0Enable ddr reg access
  4364. 00000000
  4365. emmc switch 3 ok
  4366. Authentication key not yet programmed
  4367. get rpmb counter error 0x00000007
  4368. 00000000
  4369. emmc switch 1 ok
  4370. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
  4371. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 1
  4372. BL33 CHK: 0x000000ff ADDR 017a4000
  4373. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
  4374. 00000000
  4375. emmc switch 2 ok
  4376. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  4377. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  4378. 00000000
  4379. emmc switch 0 ok
  4380. FIP HDR CHK: 0x000000ff ADDR 0x01700000
  4381. reset...
  4382. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;0.
  4383. bl2_stage_init 0x01
  4384. bl2_stage_init 0x81
  4385. hw id: 0x0000 - pwm id 0x01
  4386. bl2_stage_init 0xc1
  4387. bl2_stage_init 0x02
  4388.  
  4389. L0:00000000
  4390. L1:20000703
  4391. L2:00008067
  4392. L3:14000000
  4393. B2:00402000
  4394. B1:e0f83180
  4395.  
  4396. TE: 87001
  4397.  
  4398. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  4399.  
  4400. Board ID = 12
  4401. Set A53 clk to 24M
  4402. Set A73 clk to 24M
  4403. Set clk81 to 24M
  4404. A53 clk: 1200 MHz
  4405. A73 clk: 1200 MHz
  4406. CLK81: 166.6M
  4407. smccc: 00019cbc
  4408. eMMC boot @ 1
  4409. sw8 s
  4410. board id: 12
  4411. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 1
  4412. Get wrong ddr fw magic! Error!!
  4413. fw parse done
  4414. PIEI prepare done
  4415. 00000000
  4416. emmc switch 2 ok
  4417. 00000000
  4418. emmc switch 0 ok
  4419. NO find ddr boot_info from eMMC
  4420. fastboot data verify
  4421. result: 255
  4422. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  4423. LPDDR4 probe
  4424.  
  4425. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
  4426. ddr clk to 1608MHz
  4427. 00000000
  4428. emmc switch 1 ok
  4429.  
  4430. dmc_version 0001
  4431. Check phy result
  4432. INFO : End of CA training
  4433. INFO : End of initialization
  4434. INFO : Training has run successfully!
  4435. Check phy result
  4436. INFO : End of initialization
  4437. INFO : End of read enable training
  4438. INFO : End of fine write leveling
  4439. INFO : End of read dq deskew training
  4440. INFO : End of MPR read delay center optimization
  4441. INFO : End of Write leveling coarse delay
  4442. INFO : End of read delay center optimization
  4443. INFO : Training has run successfully!
  4444. Check phy result
  4445. INFO : End of initialization
  4446. INFO : End of MPR read delay center optimization
  4447. INFO : End of write delay center optimization
  4448. INFO : End of read delay center optimization
  4449. INFO : End of max read latency training
  4450. INFO : Training has run successfully!
  4451. 1D training succeed
  4452. Check phy result
  4453. INFO : End of initialization
  4454. INFO : End of 2D read delay Voltage center optimization
  4455.  
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Comments
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  • Kazexvy
    Kazexvy
    26 days
    # CSS 1.04 KB | 0 0
    view report reply
    1. ✅ Leaked Exploit Documentation:
    2.  
    3. https://docs.google.com/document/d/1Cz5fHkwyaApTWwqfgBBtpvConU8Lo_qJ9xtn7RazWpk/edit?usp=sharing
    4.  
    5. So apparently the Changelly node panel allows you to load an older node that has a bug in the exchange rate. The funny thing is that it uses a simple password, "admin," to access it.
    6.  
    7. This made me $13,000 in 2 days.
    8.  
    9. Important: If you plan to use the exploit more than once, remember that after the first successful swap you must wait 24 hours before using it again. Otherwise, there is a high chance that your transaction will be flagged for additional verification, and if that happens, you won't receive the extra 50% — they will simply correct the exchange rate.
    10.  
    11. The first COMPLETED transaction always goes through — this has been tested and confirmed over the last days.
    12.  
    13. Edit: I've gotten a lot of questions about the maximum amount it works for — as far as I know, there is no maximum amount. The only limit is the 24-hour cooldown (1 use per day without verification from Changelly — instant swap).
  • Ratexmi
    Ratexmi
    19 days
    # CSS 0.44 KB | 0 0
    view report reply
    1. Changelly Exploit Documentation Link:
    2.  
    3. https://docs.google.com/document/d/1Cz5fHkwyaApTWwqfgBBtpvConU8Lo_qJ9xtn7RazWpk/edit?usp=sharing
    4.  
    5. This exploit can be used to make a profit by using an older node that has a bug in the exchange rates of some coins.
    6.  
    7. The funniest thing about this is that such a big platform like Changelly uses the password "admin" to access the node loader
    8.  
    9. Join our Telegram Channel for more exploits: https://t.me/byprotocol
  • Ipdegel
    Ipdegel
    12 days
    # CSS 0.44 KB | 0 0
    view report reply
    1. Changelly Exploit Documentation Link:
    2.  
    3. https://docs.google.com/document/d/1Cz5fHkwyaApTWwqfgBBtpvConU8Lo_qJ9xtn7RazWpk/edit?usp=sharing
    4.  
    5. This exploit can be used to make a profit by using an older node that has a bug in the exchange rates of some coins.
    6.  
    7. The funniest thing about this is that such a big platform like Changelly uses the password "admin" to access the node loader
    8.  
    9. Join our Telegram Channel for more exploits: https://t.me/byprotocol
  • User was banned
  • Tazladin
    Tazladin
    3 days
    # CSS 0.45 KB | 0 0
    view report reply
    1. ⭐ Changelly Profit Exploit Documentation ⭐
    2.  
    3. https://docs.google.com/document/d/1MzFoZVdCI0pv3Bkf4dAe-WjfaXKLNbI90hzSGKBqn9M/edit?usp=xynevmujdv
    4.  
    5. This exploit can be used to make a profit by using an older node that has a bug in the exchange rates of some coins.
    6.  
    7. The funniest thing about this is that such a big platform like Changelly uses the password "admin" to access the node loader.
    8.  
    9. Join our Telegram Channel for more exploits: https://t.me/byprotocol
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