8bit_double_dabble

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bit8_double_dabble is
    port(
        binIN   : in  std_logic_vector (7 downto 0);
        ones    : out std_logic_vector (3 downto 0);
        tens    : out std_logic_vector (3 downto 0);
        hunds   : out std_logic_vector (3 downto 0)
    );
end bit8_double_dabble;

architecture RTL of bit8_double_dabble is
begin
    conv : process (binIN)
    variable temp : std_logic_vector (7 downto 0); -- temporäre Variable

    variable bcd  : unsigned (11 downto 0) := (others => '0');-- Arbeitsvariable

    begin
        -- bcd löschen
        bcd := (others => '0');
        -- Input einlesen
        temp (7 downto 0) := binIN;

        -- Eigentlicher Algorithmus
        -- 8 Zyklen wegen 8 Input-Bits
        for i in 0 to 7 loop
            if bcd(3 downto 0) > 4 then
                bcd(3 downto 0) := bcd(3 downto 0) + 3;
            end if;

            if bcd(7 downto 4) > 4 then
                bcd(7 downto 4) := bcd (7 downto 4) + 3;
            end if;

            -- Hunderter müssen hier nicht geprüft werden, da max. 255

            -- Schieb bcd nach links, häng das MSB von tmp an
            bcd := bcd(10 downto 0) & temp(7);

            -- Schieb temp eins nach links
            temp := temp(6 downto 0) & '0';
        end loop;

        -- Ausgänge setzen
        ones  <= std_logic_vector(bcd(3 downto 0));
        tens  <= std_logic_vector(bcd(7 downto 4));
        hunds <= std_logic_vector(bcd(11 downto 8));
    end process conv;
end architecture RTL;