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Sajid05

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Jan 7th, 2021
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VHDL 0.23 KB | None | 0 0
  1. -- Md. Sajid Altaf
  2. -- 180041203
  3.  
  4. if(rising_edge(clock))t
  5.    if(AB = x"FF" and IAB = '0') then
  6.             Result <= '0';
  7.     else
  8.      Result <= '1';
  9.     end if;
  10.  end if;
  11.  end process;
  12.  Output <= Result;
  13. end Behavioral;
  14.  
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