my_gates_tester

------ my_gates_tester ------
library ieee;
use ieee.std_logic_1164.all;
use work.my_gates_package.all; -- my_gates_package er inkluderet(!!)

entity my_gates_tester is
port(
    SW      : in std_logic_vector(1 downto 0);
    LEDR    : out std_logic_vector(2 downto 0));
end my_gates_tester;

architecture structural of my_gates_tester is
begin

    -- Funktionen og procesuren kaldes
    LEDR(0) <= my_xor(SW(0), SW(1));
    and_or(SW(0), SW(1), LEDR(1), LEDR(2));

end structural;