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- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- entity labZA4pkt is
- port(
- SW : IN STD_LOGIC_VECTOR(0 to 7);
- HEX0, HEX1, HEX2, HEX3, HEX4, HEX5 : OUT STD_LOGIC_VECTOR(0 to 6);
- CLK : in STD_LOGIC; -- wejscie zegarowe
- RESET : in STD_LOGIC ; -- wejscie kasowania
- SetOrDisplay : in STD_LOGIC;
- AorB : in STD_LOGIC
- );
- end labZA4pkt;
- architecture behaviour of labZA4pkt is
- signal DigitA, DigitB : std_logic_vector(0 to 7);
- function hex(SW2 : IN STD_LOGIC_VECTOR(0 to 3)) return STD_LOGIC_VECTOR is
- begin
- if (SW2 = "0000") then return "0000001";
- elsif (SW2 = "0001") then return "1001111";
- elsif (SW2 = "0010") then return "0010010";
- elsif (SW2 = "0011") then return "0000110";
- elsif (SW2 = "0100") then return "1101100";
- elsif (SW2 = "0101") then return "0100100";
- elsif (SW2 = "0110") then return "0100000";
- elsif (SW2 = "0111") then return "0001111";
- elsif (SW2 = "1000") then return "0000000";
- elsif (SW2 = "1001") then return "0000100";
- elsif (SW2 = "1010") then return "0001000"; --b
- elsif (SW2 = "1011") then return "1100000";
- elsif (SW2 = "1100") then return "0110001";
- elsif (SW2 = "1101") then return "1000010";
- elsif (SW2 = "1110") then return "0110000";
- else return "0111000";
- end if;
- end hex;
- begin
- p:process(RESET, CLK) is
- begin
- HEX2 <= "0000100";
- HEX5 <= "0001000";
- if RESET = '0' then
- HEX0 <= "1111111"; -- "0000001"
- HEX1 <= "1111111";
- HEX3 <= "1111111";
- HEX4 <= "1111111";
- DigitA <= "UUUUUUUU";
- DigitB <= "UUUUUUUU";
- elsif (CLK='1' and CLK'event) then
- if (SetOrDisplay = '0') then
- if (AorB = '0') then DigitA <= SW;
- elsif (AorB = '1') then DigitB <= Sw;
- end if;
- elsif (SetOrDisplay = '1') then
- if (AorB = '0') then
- HEX0 <= hex(DigitA(0 to 3));
- HEX1 <= hex(DigitA(4 to 7));
- elsif (AorB = '1') then
- HEX4 <= hex(DigitB(0 to 3));
- HEX3 <= hex(DigitB(4 to 7));
- end if;
- end if;
- end if;
- end process;
- end behaviour;
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