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VHDL 2.06 KB | None | 0 0
  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer: Nabil Sayegh
  4. --
  5. -- Create Date:    12:11:03 08/07/2009
  6. -- Design Name:
  7. -- Module Name:    fifo_fwft - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library ieee;
  21.   use ieee.std_logic_1164.all;
  22.   use ieee.numeric_std.all;
  23.  
  24. entity fifo_fwft is
  25.     generic
  26.     (
  27.     addr_width : Integer := 8;
  28.     data_width : Integer := 8
  29.     );
  30.     port
  31.     (
  32.         clock              : IN  std_logic;
  33.         reset              : IN  std_logic;
  34.  
  35.         wren               : IN  std_logic;
  36.         rdack              : IN  std_logic;
  37.         din                : IN  std_logic_vector(data_width-1 downto 0);
  38.         dout               : OUT std_logic_vector(data_width-1 downto 0);
  39.         empty              : OUT std_logic;
  40.         almost_full        : OUT std_logic
  41.     );
  42. end entity fifo_fwft;
  43.  
  44. architecture Behavioral of fifo_fwft is
  45.     signal rden : std_logic;
  46.     signal flag : std_logic;
  47. begin
  48.  
  49.     Inst_fifo: entity work.fifo_simple
  50.     generic MAP
  51.     (
  52.     addr_width => addr_width,
  53.     data_width => data_width
  54.     )
  55.     port map
  56.     (
  57.         clock => clock,
  58.         reset => reset,
  59.         wren => wren,
  60.         rden => rden,
  61.         din => din,
  62.         dout => dout,
  63.         empty => empty,
  64.         almost_full => almost_full
  65.     );
  66.  
  67.     rden <= (not flag and not empty) or rdack;
  68.     process (clock, reset)
  69.     begin
  70.         if rising_edge(clock) then
  71.             flag <= (flag and not rdack) or (not empty);
  72.         end if;
  73.     end process;
  74.  
  75. end architecture Behavioral;
  76.  
  77.  
  78. ERROR:HDLParsers:1411 - "C:/Dokumente und Einstellungen/All Users/Dokumente/ssp/trunk/fifo_fwft.vhd" Line 67. Parameter empty of mode out can not be associated with a formal parameter of mode in.
  79. ERROR:HDLParsers:1411 - "C:/Dokumente und Einstellungen/All Users/Dokumente/ssp/trunk/fifo_fwft.vhd" Line 71. Parameter empty of mode out can not be associated with a formal parameter of mode in.
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