LucaSkywalker

SevenCounter_tb.vhd

Nov 21st, 2020
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  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.std_logic_arith.all;
  4. use IEEE.std_logic_misc.all;
  5. use IEEE.std_logic_unsigned.all;
  6.  
  7. ENTITY SevenCounter_tb IS
  8.     port (  Clk_out : OUT STD_LOGIC;
  9.                 rst_out: OUT STD_LOGIC;
  10.                 pData_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  11.                 pData_en_out: OUT STD_LOGIC;
  12.                 BCD_mode_out: OUT STD_LOGIC;
  13.                 CNTR_en_out: OUT STD_LOGIC);
  14. END SevenCounter_tb;
  15.  
  16. ARCHITECTURE behavior OF SevenCounter_tb IS
  17.  
  18. constant Clk_period : time := 10 ns;
  19.  BEGIN
  20.              
  21.    Clk_process :process
  22.    begin
  23.         Clk_out <= '0';
  24.         wait for Clk_period/2;
  25.         Clk_out <= '1';
  26.         wait for Clk_period/2;
  27.    end process;
  28.  
  29.    stim_proc: process
  30.    begin
  31.         pData_en_out <= '0';
  32.         CNTR_en_out <= '1';
  33.         BCD_mode_out <= '1';
  34.         pData_out <= "0011";
  35.         rst_out <= '1';
  36.         wait for 8 ns;
  37.         rst_out <= '0';
  38.         wait for 50 ns;
  39.         CNTR_en_out <= '0';
  40.         wait for 20 ns;
  41.         CNTR_en_out <= '1';
  42.         wait for 30 ns;
  43.         pData_en_out <= '1';
  44.         wait for 10 ns;
  45.         pData_en_out <= '0';
  46.         wait for 100 ns;
  47.         BCD_mode_out <= '0';
  48.         wait;
  49.    end process;
  50. END;
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