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  1. /*
  2.  * Copyright (c) 2017 MediaTek Inc.
  3.  * Author: John Crispin <john@phrozen.org>
  4.  *     Sean Wang <sean.wang@mediatek.com>
  5.  *
  6.  * This program is free software; you can redistribute it and/or modify
  7.  * it under the terms of the GNU General Public License version 2 as
  8.  * published by the Free Software Foundation.
  9.  *
  10.  * This program is distributed in the hope that it will be useful,
  11.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13.  * GNU General Public License for more details.
  14.  */
  15.  
  16. #include <dt-bindings/interrupt-controller/irq.h>
  17. #include <dt-bindings/interrupt-controller/arm-gic.h>
  18. #include <dt-bindings/clock/mt2701-clk.h>
  19. #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
  20. #include <dt-bindings/power/mt2701-power.h>
  21. #include <dt-bindings/gpio/gpio.h>
  22. #include <dt-bindings/phy/phy.h>
  23. #include <dt-bindings/reset/mt2701-resets.h>
  24. #include <dt-bindings/thermal/thermal.h>
  25.  
  26. / {
  27.     compatible = "mediatek,mt7623";
  28.     interrupt-parent = <&sysirq>;
  29.     #address-cells = <2>;
  30.     #size-cells = <2>;
  31.  
  32.     cpu_opp_table: opp_table {
  33.         compatible = "operating-points-v2";
  34.         opp-shared;
  35.  
  36.         opp-98000000 {
  37.             opp-hz = /bits/ 64 <98000000>;
  38.             opp-microvolt = <1050000>;
  39.         };
  40.  
  41.         opp-198000000 {
  42.             opp-hz = /bits/ 64 <198000000>;
  43.             opp-microvolt = <1050000>;
  44.         };
  45.  
  46.         opp-398000000 {
  47.             opp-hz = /bits/ 64 <398000000>;
  48.             opp-microvolt = <1050000>;
  49.         };
  50.  
  51.         opp-598000000 {
  52.             opp-hz = /bits/ 64 <598000000>;
  53.             opp-microvolt = <1050000>;
  54.         };
  55.  
  56.         opp-747500000 {
  57.             opp-hz = /bits/ 64 <747500000>;
  58.             opp-microvolt = <1050000>;
  59.         };
  60.  
  61.         opp-1040000000 {
  62.             opp-hz = /bits/ 64 <1040000000>;
  63.             opp-microvolt = <1150000>;
  64.         };
  65.  
  66.         opp-1196000000 {
  67.             opp-hz = /bits/ 64 <1196000000>;
  68.             opp-microvolt = <1200000>;
  69.         };
  70.  
  71.         opp-1300000000 {
  72.             opp-hz = /bits/ 64 <1300000000>;
  73.             opp-microvolt = <1300000>;
  74.         };
  75.     };
  76.  
  77.     cpus {
  78.         #address-cells = <1>;
  79.         #size-cells = <0>;
  80.         enable-method = "mediatek,mt6589-smp";
  81.  
  82.         cpu0: cpu@0 {
  83.             device_type = "cpu";
  84.             compatible = "arm,cortex-a7";
  85.             reg = <0x0>;
  86.             clocks = <&infracfg CLK_INFRA_CPUSEL>,
  87.                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  88.             clock-names = "cpu", "intermediate";
  89.             operating-points-v2 = <&cpu_opp_table>;
  90.             #cooling-cells = <2>;
  91.             cooling-min-level = <0>;
  92.             cooling-max-level = <7>;
  93.             clock-frequency = <1300000000>;
  94.         };
  95.  
  96.         cpu1: cpu@1 {
  97.             device_type = "cpu";
  98.             compatible = "arm,cortex-a7";
  99.             reg = <0x1>;
  100.             operating-points-v2 = <&cpu_opp_table>;
  101.             #cooling-cells = <2>;
  102.             clock-frequency = <1300000000>;
  103.         };
  104.  
  105.         cpu2: cpu@2 {
  106.             device_type = "cpu";
  107.             compatible = "arm,cortex-a7";
  108.             reg = <0x2>;
  109.             operating-points-v2 = <&cpu_opp_table>;
  110.             #cooling-cells = <2>;
  111.             clock-frequency = <1300000000>;
  112.         };
  113.  
  114.         cpu3: cpu@3 {
  115.             device_type = "cpu";
  116.             compatible = "arm,cortex-a7";
  117.             reg = <0x3>;
  118.             operating-points-v2 = <&cpu_opp_table>;
  119.             #cooling-cells = <2>;
  120.             clock-frequency = <1300000000>;
  121.         };
  122.     };
  123.  
  124.     system_clk: dummy13m {
  125.         compatible = "fixed-clock";
  126.         clock-frequency = <13000000>;
  127.         #clock-cells = <0>;
  128.     };
  129.  
  130.     rtc32k: oscillator@1 {
  131.         compatible = "fixed-clock";
  132.         #clock-cells = <0>;
  133.         clock-frequency = <32000>;
  134.         clock-output-names = "rtc32k";
  135.     };
  136.  
  137.     clk26m: oscillator@0 {
  138.         compatible = "fixed-clock";
  139.         #clock-cells = <0>;
  140.         clock-frequency = <26000000>;
  141.         clock-output-names = "clk26m";
  142.     };
  143.  
  144.     thermal-zones {
  145.             cpu_thermal: cpu_thermal {
  146.                 polling-delay-passive = <1000>;
  147.                 polling-delay = <1000>;
  148.  
  149.                 thermal-sensors = <&thermal 0>;
  150.  
  151.                 trips {
  152.                     cpu_passive: cpu_passive {
  153.                         temperature = <47000>;
  154.                         hysteresis = <2000>;
  155.                         type = "passive";
  156.                     };
  157.  
  158.                     cpu_active: cpu_active {
  159.                         temperature = <67000>;
  160.                         hysteresis = <2000>;
  161.                         type = "active";
  162.                     };
  163.  
  164.                     cpu_hot: cpu_hot {
  165.                         temperature = <87000>;
  166.                         hysteresis = <2000>;
  167.                         type = "hot";
  168.                     };
  169.  
  170.                     cpu_crit {
  171.                         temperature = <107000>;
  172.                         hysteresis = <2000>;
  173.                         type = "critical";
  174.                     };
  175.                 };
  176.  
  177.             cooling-maps {
  178.                 map0 {
  179.                     trip = <&cpu_passive>;
  180.                     cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  181.                 };
  182.  
  183.                 map1 {
  184.                     trip = <&cpu_active>;
  185.                     cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  186.                 };
  187.  
  188.                 map2 {
  189.                     trip = <&cpu_hot>;
  190.                     cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  191.                 };
  192.             };
  193.         };
  194.     };
  195.  
  196.     timer {
  197.         compatible = "arm,armv7-timer";
  198.         interrupt-parent = <&gic>;
  199.         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  200.                  <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  201.                  <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  202.                  <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  203.         clock-frequency = <13000000>;
  204.         arm,cpu-registers-not-fw-configured;
  205.     };
  206.  
  207.     topckgen: syscon@10000000 {
  208.         compatible = "mediatek,mt7623-topckgen",
  209.                  "mediatek,mt2701-topckgen",
  210.                  "syscon";
  211.         reg = <0 0x10000000 0 0x1000>;
  212.         #clock-cells = <1>;
  213.     };
  214.  
  215.     infracfg: syscon@10001000 {
  216.         compatible = "mediatek,mt7623-infracfg",
  217.                  "mediatek,mt2701-infracfg",
  218.                  "syscon";
  219.         reg = <0 0x10001000 0 0x1000>;
  220.         #clock-cells = <1>;
  221.         #reset-cells = <1>;
  222.     };
  223.  
  224.     pericfg: syscon@10003000 {
  225.         compatible =  "mediatek,mt7623-pericfg",
  226.                   "mediatek,mt2701-pericfg",
  227.                   "syscon";
  228.         reg = <0 0x10003000 0 0x1000>;
  229.         #clock-cells = <1>;
  230.         #reset-cells = <1>;
  231.     };
  232.  
  233.     pio: pinctrl@10005000 {
  234.         compatible = "mediatek,mt7623-pinctrl",
  235.                  "mediatek,mt2701-pinctrl";
  236.         reg = <0 0x1000b000 0 0x1000>;
  237.         mediatek,pctl-regmap = <&syscfg_pctl_a>;
  238.         pins-are-numbered;
  239.         gpio-controller;
  240.         #gpio-cells = <2>;
  241.         interrupt-controller;
  242.         interrupt-parent = <&gic>;
  243.         #interrupt-cells = <2>;
  244.         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
  245.                  <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
  246.     };
  247.  
  248.     syscfg_pctl_a: syscfg@10005000 {
  249.         compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
  250.         reg = <0 0x10005000 0 0x1000>;
  251.     };
  252.  
  253.     scpsys: scpsys@10006000 {
  254.         compatible = "mediatek,mt7623-scpsys",
  255.                  "mediatek,mt2701-scpsys",
  256.                  "syscon";
  257.         #power-domain-cells = <1>;
  258.         reg = <0 0x10006000 0 0x1000>;
  259.         infracfg = <&infracfg>;
  260.         clocks = <&topckgen CLK_TOP_MM_SEL>,
  261.              <&topckgen CLK_TOP_MFG_SEL>,
  262.              <&topckgen CLK_TOP_ETHIF_SEL>;
  263.         clock-names = "mm", "mfg", "ethif";
  264.     };
  265.  
  266.     watchdog: watchdog@10007000 {
  267.         compatible = "mediatek,mt7623-wdt",
  268.                  "mediatek,mt6589-wdt";
  269.         reg = <0 0x10007000 0 0x100>;
  270.         interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_FALLING>;
  271.         #reset-cells = <1>;
  272.     };
  273.  
  274.     timer: timer@10008000 {
  275.         compatible = "mediatek,mt7623-timer",
  276.                  "mediatek,mt6577-timer";
  277.         reg = <0 0x10008000 0 0x80>;
  278.         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
  279.         clocks = <&system_clk>, <&rtc32k>;
  280.         clock-names = "system-clk", "rtc-clk";
  281.     };
  282.     pwrap: pwrap@1000d000 {
  283.         compatible = "mediatek,mt7623-pwrap",
  284.                  "mediatek,mt2701-pwrap";
  285.         reg = <0 0x1000d000 0 0x1000>;
  286.         reg-names = "pwrap";
  287.         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
  288.         resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
  289.         reset-names = "pwrap";
  290.         clocks = <&infracfg CLK_INFRA_PMICSPI>,
  291.              <&infracfg CLK_INFRA_PMICWRAP>;
  292.         clock-names = "spi", "wrap";
  293.     };
  294.  
  295.     cir: cir@10013000 {
  296.         compatible = "mediatek,mt7623-cir";
  297.         reg = <0 0x10013000 0 0x1000>;
  298.         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
  299.         clocks = <&infracfg CLK_INFRA_IRRX>;
  300.         clock-names = "clk";
  301.         status = "disabled";
  302.     };
  303.  
  304.     sysirq: interrupt-controller@10200100 {
  305.         compatible = "mediatek,mt7623-sysirq",
  306.                  "mediatek,mt6577-sysirq";
  307.         interrupt-controller;
  308.         #interrupt-cells = <3>;
  309.         interrupt-parent = <&gic>;
  310.         reg = <0 0x10200100 0 0x1c>;
  311.     };
  312.  
  313.     efuse: efuse@10206000 {
  314.         compatible = "mediatek,mt7623-efuse",
  315.                  "mediatek,mt8173-efuse";
  316.         reg = <0 0x10206000 0 0x1000>;
  317.         #address-cells = <1>;
  318.         #size-cells = <1>;
  319.         thermal_calibration_data: calib@424 {
  320.             reg = <0x424 0xc>;
  321.         };
  322.     };
  323.  
  324.     apmixedsys: syscon@10209000 {
  325.         compatible = "mediatek,mt7623-apmixedsys",
  326.                  "mediatek,mt2701-apmixedsys",
  327.                  "syscon";
  328.         reg = <0 0x10209000 0 0x1000>;
  329.         #clock-cells = <1>;
  330.         #reset-cells = <1>;
  331.     };
  332.  
  333.     rng: rng@1020f000 {
  334.         compatible = "mediatek,mt7623-rng";
  335.         reg = <0 0x1020f000 0 0x1000>;
  336.         clocks = <&infracfg CLK_INFRA_TRNG>;
  337.         clock-names = "rng";
  338.     };
  339.  
  340.     gic: interrupt-controller@10211000 {
  341.         compatible = "arm,cortex-a7-gic";
  342.         interrupt-controller;
  343.         #interrupt-cells = <3>;
  344.         interrupt-parent = <&gic>;
  345.         reg = <0 0x10211000 0 0x1000>,
  346.               <0 0x10212000 0 0x2000>,
  347.               <0 0x10214000 0 0x2000>,
  348.               <0 0x10216000 0 0x2000>;
  349.     };
  350.  
  351.     auxadc: adc@11001000 {
  352.         compatible = "mediatek,mt7623-auxadc",
  353.                  "mediatek,mt2701-auxadc";
  354.         reg = <0 0x11001000 0 0x1000>;
  355.         clocks = <&pericfg CLK_PERI_AUXADC>;
  356.         clock-names = "main";
  357.         #io-channel-cells = <1>;
  358.     };
  359.  
  360.     uart2: serial@11004000 {
  361.         compatible = "mediatek,mt7623-uart",
  362.                  "mediatek,mt6577-uart";
  363.         reg = <0 0x11004000 0 0x400>;
  364.         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
  365.         clocks = <&pericfg CLK_PERI_UART2_SEL>,
  366.              <&pericfg CLK_PERI_UART2>;
  367.         clock-names = "baud", "bus";
  368.         status = "disabled";
  369.     };
  370.     uart0: serial@11002000 {
  371.         compatible = "mediatek,mt7623-uart",
  372.                  "mediatek,mt6577-uart";
  373.         reg = <0 0x11002000 0 0x400>;
  374.         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
  375.         clocks = <&pericfg CLK_PERI_UART0_SEL>,
  376.              <&pericfg CLK_PERI_UART0>;
  377.         clock-names = "baud", "bus";
  378.         status = "disabled";
  379.     };
  380.  
  381.     uart1: serial@11003000 {
  382.         compatible = "mediatek,mt7623-uart",
  383.                  "mediatek,mt6577-uart";
  384.         reg = <0 0x11003000 0 0x400>;
  385.         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
  386.         clocks = <&pericfg CLK_PERI_UART1_SEL>,
  387.              <&pericfg CLK_PERI_UART1>;
  388.         clock-names = "baud", "bus";
  389.         status = "disabled";
  390.     };
  391.  
  392.     uart3: serial@11005000 {
  393.         compatible = "mediatek,mt7623-uart",
  394.                  "mediatek,mt6577-uart";
  395.         reg = <0 0x11005000 0 0x400>;
  396.         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
  397.         clocks = <&pericfg CLK_PERI_UART3_SEL>,
  398.              <&pericfg CLK_PERI_UART3>;
  399.         clock-names = "baud", "bus";
  400.         status = "disabled";
  401.     };
  402.  
  403.     pwm: pwm@11006000 {
  404.         compatible = "mediatek,mt7623-pwm";
  405.         reg = <0 0x11006000 0 0x1000>;
  406.         #pwm-cells = <2>;
  407.         clocks = <&topckgen CLK_TOP_PWM_SEL>,
  408.              <&pericfg CLK_PERI_PWM>,
  409.              <&pericfg CLK_PERI_PWM1>,
  410.              <&pericfg CLK_PERI_PWM2>,
  411.              <&pericfg CLK_PERI_PWM3>,
  412.              <&pericfg CLK_PERI_PWM4>,
  413.              <&pericfg CLK_PERI_PWM5>;
  414.         clock-names = "top", "main", "pwm1", "pwm2",
  415.                   "pwm3", "pwm4", "pwm5";
  416.         status = "disabled";
  417.     };
  418.  
  419.     i2c0: i2c@11007000 {
  420.         compatible = "mediatek,mt7623-i2c",
  421.                  "mediatek,mt6577-i2c";
  422.         reg = <0 0x11007000 0 0x70>,
  423.               <0 0x11000200 0 0x80>;
  424.         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
  425.         clock-div = <16>;
  426.         clocks = <&pericfg CLK_PERI_I2C0>,
  427.              <&pericfg CLK_PERI_AP_DMA>;
  428.         clock-names = "main", "dma";
  429.         #address-cells = <1>;
  430.         #size-cells = <0>;
  431.         status = "disabled";
  432.     };
  433.  
  434.     i2c1: i2c@11008000 {
  435.         compatible = "mediatek,mt7623-i2c",
  436.                  "mediatek,mt6577-i2c";
  437.         reg = <0 0x11008000 0 0x70>,
  438.               <0 0x11000280 0 0x80>;
  439.         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
  440.         clock-div = <16>;
  441.         clocks = <&pericfg CLK_PERI_I2C1>,
  442.              <&pericfg CLK_PERI_AP_DMA>;
  443.         clock-names = "main", "dma";
  444.         #address-cells = <1>;
  445.         #size-cells = <0>;
  446.         status = "disabled";
  447.     };
  448.  
  449.     i2c2: i2c@11009000 {
  450.         compatible = "mediatek,mt7623-i2c",
  451.                  "mediatek,mt6577-i2c";
  452.         reg = <0 0x11009000 0 0x70>,
  453.               <0 0x11000300 0 0x80>;
  454.         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
  455.         clock-div = <16>;
  456.         clocks = <&pericfg CLK_PERI_I2C2>,
  457.              <&pericfg CLK_PERI_AP_DMA>;
  458.         clock-names = "main", "dma";
  459.         #address-cells = <1>;
  460.         #size-cells = <0>;
  461.         status = "disabled";
  462.     };
  463.  
  464.     spi0: spi@1100a000 {
  465.         compatible = "mediatek,mt7623-spi",
  466.                  "mediatek,mt2701-spi";
  467.         #address-cells = <1>;
  468.         #size-cells = <0>;
  469.         reg = <0 0x1100a000 0 0x100>;
  470.         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
  471.         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
  472.              <&topckgen CLK_TOP_SPI0_SEL>,
  473.              <&pericfg CLK_PERI_SPI0>;
  474.         clock-names = "parent-clk", "sel-clk", "spi-clk";
  475.         status = "disabled";
  476.     };
  477.  
  478.     thermal: thermal@1100b000 {
  479.         #thermal-sensor-cells = <1>;
  480.         compatible = "mediatek,mt7623-thermal",
  481.                  "mediatek,mt2701-thermal";
  482.         reg = <0 0x1100b000 0 0x1000>;
  483.         interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
  484.         clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
  485.         clock-names = "therm", "auxadc";
  486.         resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
  487.         reset-names = "therm";
  488.         mediatek,auxadc = <&auxadc>;
  489.         mediatek,apmixedsys = <&apmixedsys>;
  490.         nvmem-cells = <&thermal_calibration_data>;
  491.         nvmem-cell-names = "calibration-data";
  492.     };
  493.  
  494.     btif_tx: btif_tx@11000780 {
  495.         compatible = "mediatek,btif_tx";
  496.         reg = <0 0x11000780 0 0x80>;
  497.         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
  498.         status = "okay";
  499.     };
  500.  
  501.     btif_rx: btif_rx@11000800 {
  502.         compatible = "mediatek,btif_rx";
  503.         reg = <0 0x11000800 0 0x80>;
  504.         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
  505.         status = "okay";
  506.     };
  507.  
  508.     btif: btif@1100c000 {
  509.         compatible = "mediatek,btif";
  510.         reg = <0 0x1100c000 0 0x1000>;
  511.         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
  512.         clocks = <&pericfg CLK_PERI_BTIF>, <&pericfg CLK_PERI_AP_DMA>;
  513.         clock-names = "btifc", "apdmac";
  514.         status = "okay";
  515.     };
  516.  
  517.     nandc: nfi@1100d000 {
  518.         compatible = "mediatek,mt7623-nfc",
  519.                  "mediatek,mt2701-nfc";
  520.         reg = <0 0x1100d000 0 0x1000>;
  521.         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
  522.         power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
  523.         clocks = <&pericfg CLK_PERI_NFI>,
  524.              <&pericfg CLK_PERI_NFI_PAD>;
  525.         clock-names = "nfi_clk", "pad_clk";
  526.         status = "disabled";
  527.         ecc-engine = <&bch>;
  528.         #address-cells = <1>;
  529.         #size-cells = <0>;
  530.     };
  531.  
  532.     bch: ecc@1100e000 {
  533.         compatible = "mediatek,mt7623-ecc",
  534.                  "mediatek,mt2701-ecc";
  535.         reg = <0 0x1100e000 0 0x1000>;
  536.         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
  537.         clocks = <&pericfg CLK_PERI_NFI_ECC>;
  538.         clock-names = "nfiecc_clk";
  539.         status = "disabled";
  540.     };
  541.  
  542.     spi1: spi@11016000 {
  543.         compatible = "mediatek,mt7623-spi",
  544.                  "mediatek,mt2701-spi";
  545.         #address-cells = <1>;
  546.         #size-cells = <0>;
  547.         reg = <0 0x11016000 0 0x100>;
  548.         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
  549.         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
  550.              <&topckgen CLK_TOP_SPI1_SEL>,
  551.              <&pericfg CLK_PERI_SPI1>;
  552.         clock-names = "parent-clk", "sel-clk", "spi-clk";
  553.         status = "disabled";
  554.     };
  555.  
  556.     spi2: spi@11017000 {
  557.         compatible = "mediatek,mt7623-spi",
  558.                  "mediatek,mt2701-spi";
  559.         #address-cells = <1>;
  560.         #size-cells = <0>;
  561.         reg = <0 0x11017000 0 0x1000>;
  562.         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
  563.         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
  564.              <&topckgen CLK_TOP_SPI2_SEL>,
  565.              <&pericfg CLK_PERI_SPI2>;
  566.         clock-names = "parent-clk", "sel-clk", "spi-clk";
  567.         status = "disabled";
  568.     };
  569.  
  570.     afe: audio-controller@11220000 {
  571.         compatible = "mediatek,mt7623-audio",
  572.                  "mediatek,mt2701-audio";
  573.         reg = <0 0x11220000 0 0x2000>,
  574.               <0 0x112a0000 0 0x20000>;
  575.         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
  576.         power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
  577.  
  578.         clocks = <&infracfg CLK_INFRA_AUDIO>,
  579.              <&topckgen CLK_TOP_AUD_MUX1_SEL>,
  580.              <&topckgen CLK_TOP_AUD_MUX2_SEL>,
  581.              <&topckgen CLK_TOP_AUD_MUX1_DIV>,
  582.              <&topckgen CLK_TOP_AUD_MUX2_DIV>,
  583.              <&topckgen CLK_TOP_AUD_48K_TIMING>,
  584.              <&topckgen CLK_TOP_AUD_44K_TIMING>,
  585.              <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
  586.              <&topckgen CLK_TOP_APLL_SEL>,
  587.              <&topckgen CLK_TOP_AUD1PLL_98M>,
  588.              <&topckgen CLK_TOP_AUD2PLL_90M>,
  589.              <&topckgen CLK_TOP_HADDS2PLL_98M>,
  590.              <&topckgen CLK_TOP_HADDS2PLL_294M>,
  591.              <&topckgen CLK_TOP_AUDPLL>,
  592.              <&topckgen CLK_TOP_AUDPLL_D4>,
  593.              <&topckgen CLK_TOP_AUDPLL_D8>,
  594.              <&topckgen CLK_TOP_AUDPLL_D16>,
  595.              <&topckgen CLK_TOP_AUDPLL_D24>,
  596.              <&topckgen CLK_TOP_AUDINTBUS_SEL>,
  597.              <&clk26m>,
  598.              <&topckgen CLK_TOP_SYSPLL1_D4>,
  599.              <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
  600.              <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
  601.              <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
  602.              <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
  603.              <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
  604.              <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
  605.              <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
  606.              <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
  607.              <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
  608.              <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
  609.              <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
  610.              <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
  611.              <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
  612.              <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
  613.              <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
  614.              <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
  615.              <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
  616.              <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
  617.              <&topckgen CLK_TOP_ASM_M_SEL>,
  618.              <&topckgen CLK_TOP_ASM_H_SEL>,
  619.              <&topckgen CLK_TOP_UNIVPLL2_D4>,
  620.              <&topckgen CLK_TOP_UNIVPLL2_D2>,
  621.              <&topckgen CLK_TOP_SYSPLL_D5>;
  622.  
  623.         clock-names = "infra_sys_audio_clk",
  624.              "top_audio_mux1_sel",
  625.              "top_audio_mux2_sel",
  626.              "top_audio_mux1_div",
  627.              "top_audio_mux2_div",
  628.              "top_audio_48k_timing",
  629.              "top_audio_44k_timing",
  630.              "top_audpll_mux_sel",
  631.              "top_apll_sel",
  632.              "top_aud1_pll_98M",
  633.              "top_aud2_pll_90M",
  634.              "top_hadds2_pll_98M",
  635.              "top_hadds2_pll_294M",
  636.              "top_audpll",
  637.              "top_audpll_d4",
  638.              "top_audpll_d8",
  639.              "top_audpll_d16",
  640.              "top_audpll_d24",
  641.              "top_audintbus_sel",
  642.              "clk_26m",
  643.              "top_syspll1_d4",
  644.              "top_aud_k1_src_sel",
  645.              "top_aud_k2_src_sel",
  646.              "top_aud_k3_src_sel",
  647.              "top_aud_k4_src_sel",
  648.              "top_aud_k5_src_sel",
  649.              "top_aud_k6_src_sel",
  650.              "top_aud_k1_src_div",
  651.              "top_aud_k2_src_div",
  652.              "top_aud_k3_src_div",
  653.              "top_aud_k4_src_div",
  654.              "top_aud_k5_src_div",
  655.              "top_aud_k6_src_div",
  656.              "top_aud_i2s1_mclk",
  657.              "top_aud_i2s2_mclk",
  658.              "top_aud_i2s3_mclk",
  659.              "top_aud_i2s4_mclk",
  660.              "top_aud_i2s5_mclk",
  661.              "top_aud_i2s6_mclk",
  662.              "top_asm_m_sel",
  663.              "top_asm_h_sel",
  664.              "top_univpll2_d4",
  665.              "top_univpll2_d2",
  666.              "top_syspll_d5";
  667.     };
  668.  
  669.     mmc0: mmc@11230000 {
  670.         compatible = "mediatek,mt7623-mmc",
  671.                  "mediatek,mt2701-mmc";
  672.         reg = <0 0x11230000 0 0x1000>;
  673.         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
  674.         clocks = <&pericfg CLK_PERI_MSDC30_0>,
  675.              <&topckgen CLK_TOP_MSDC30_0_SEL>;
  676.         clock-names = "source", "hclk";
  677.         status = "disabled";
  678.     };
  679.  
  680.     consys: consys@18070000 {
  681.         compatible = "mediatek,mt7623-consys";
  682.         reg = <0 0x18070000 0 0x0200>,  /*CONN_MCU_CONFIG_BASE      */
  683.             <0 0x10001000 0 0x1600>;  /*TOPCKGEN_BASE             */
  684.         clocks = <&infracfg CLK_INFRA_CONNMCU>;
  685.         clock-names = "consysbus";
  686.         power-domains = <&scpsys MT2701_POWER_DOMAIN_CONN>;
  687.         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>,  /* BGF_EINT */
  688.                     <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>;  /* WDT_EINT */
  689.         resets = <&watchdog MT2701_TOPRGU_CONN_MCU_RST>;
  690.         reset-names = "connsys";
  691.         status="disabled";
  692.     };
  693.  
  694.     wifi:wifi@180f0000 {
  695.         compatible = "mediatek,mt7623-wifi",
  696.                     "mediatek,wifi";
  697.         reg = <0 0x180f0000 0 0x005c>;
  698.         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
  699.         clocks = <&pericfg CLK_PERI_AP_DMA>;
  700.         clock-names = "wifi-dma";
  701.     };
  702.    
  703.     mmc1: mmc@11240000 {
  704.         compatible = "mediatek,mt7623-mmc",
  705.                  "mediatek,mt2701-mmc";
  706.         reg = <0 0x11240000 0 0x1000>;
  707.         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
  708.         clocks = <&pericfg CLK_PERI_MSDC30_1>,
  709.              <&topckgen CLK_TOP_MSDC30_1_SEL>;
  710.         clock-names = "source", "hclk";
  711.         status = "disabled";
  712.     };
  713.  
  714.     hifsys: syscon@1a000000 {
  715.         compatible = "mediatek,mt7623-hifsys",
  716.                  "mediatek,mt2701-hifsys",
  717.                  "syscon";
  718.         reg = <0 0x1a000000 0 0x1000>;
  719.         #clock-cells = <1>;
  720.         #reset-cells = <1>;
  721.     };
  722.  
  723.         pcie: pcie-controller@1a140000 {
  724.                 compatible = "mediatek,mt7623-pcie";
  725.                 device_type = "pci";
  726.                 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
  727.                       <0 0x1a142000 0 0x1000>, /* Port0 registers */
  728.                       <0 0x1a143000 0 0x1000>, /* Port1 registers */
  729.                       <0 0x1a144000 0 0x1000>; /* Port2 registers */
  730.                 reg-names = "subsys", "port0", "port1", "port2";
  731.                 #address-cells = <3>;
  732.                 #size-cells = <2>;
  733.                 #interrupt-cells = <1>;
  734.                 interrupt-map-mask = <0xf800 0 0 0>;
  735.                 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
  736.                                 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
  737.                                 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
  738.                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
  739.                          <&hifsys CLK_HIFSYS_PCIE0>,
  740.                          <&hifsys CLK_HIFSYS_PCIE1>,
  741.                          <&hifsys CLK_HIFSYS_PCIE2>;
  742.                 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
  743.                 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
  744.                          <&hifsys MT2701_HIFSYS_PCIE1_RST>,
  745.                          <&hifsys MT2701_HIFSYS_PCIE2_RST>;
  746.                 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
  747.                 phys = <&pcie0_port PHY_TYPE_PCIE>,
  748.                        <&pcie1_port PHY_TYPE_PCIE>,
  749.                        <&u3port1 PHY_TYPE_PCIE>;
  750.                 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
  751.                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
  752.                 bus-range = <0x00 0xff>;
  753.                 status = "disabled";
  754.                 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
  755.                           0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
  756.  
  757.                 pcie@0,0 {
  758.                         device_type = "pci";
  759.                         reg = <0x0000 0 0 0 0>;
  760.                         #address-cells = <3>;
  761.                         #size-cells = <2>;
  762.                         #interrupt-cells = <1>;
  763.                         interrupt-map-mask = <0 0 0 0>;
  764.                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
  765.                         ranges;
  766.                         num-lanes = <1>;
  767.                         status = "disabled";
  768.                 };
  769.  
  770.                 pcie@1,0 {
  771.                         device_type = "pci";
  772.                         reg = <0x0800 0 0 0 0>;
  773.                         #address-cells = <3>;
  774.                         #size-cells = <2>;
  775.                         #interrupt-cells = <1>;
  776.                         interrupt-map-mask = <0 0 0 0>;
  777.                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
  778.                         ranges;
  779.                         num-lanes = <1>;
  780.                         status = "disabled";
  781.                 };
  782.  
  783.                 pcie@2,0 {
  784.                         device_type = "pci";
  785.                         reg = <0x1000 0 0 0 0>;
  786.                         #address-cells = <3>;
  787.                         #size-cells = <2>;
  788.                         #interrupt-cells = <1>;
  789.                         interrupt-map-mask = <0 0 0 0>;
  790.                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
  791.                         ranges;
  792.                         num-lanes = <1>;
  793.                         status = "disabled";
  794.                 };
  795.         };
  796.         pcie0_phy: pcie-phy@1a149000 {
  797.                 compatible = "mediatek,generic-tphy-v1";
  798.                 reg = <0 0x1a149000 0 0x0700>;
  799.                 #address-cells = <2>;
  800.                 #size-cells = <2>;
  801.                 ranges;
  802.                 status = "disabled";
  803.  
  804.                 pcie0_port: pcie-phy@1a149900 {
  805.                         reg = <0 0x1a149900 0 0x0700>;
  806.                         clocks = <&clk26m>;
  807.                         clock-names = "ref";
  808.                         #phy-cells = <1>;
  809.                         status = "okay";
  810.                 };
  811.         };
  812.  
  813.         pcie1_phy: pcie-phy@1a14a000 {
  814.                 compatible = "mediatek,generic-tphy-v1";
  815.                 reg = <0 0x1a14a000 0 0x0700>;
  816.                 #address-cells = <2>;
  817.                 #size-cells = <2>;
  818.                 ranges;
  819.                 status = "disabled";
  820.  
  821.                 pcie1_port: pcie-phy@1a14a900 {
  822.                         reg = <0 0x1a14a900 0 0x0700>;
  823.                         clocks = <&clk26m>;
  824.                         clock-names = "ref";
  825.                         #phy-cells = <1>;
  826.                         status = "okay";
  827.                 };
  828.         };
  829.  
  830.     usb1: usb@1a1c0000 {
  831.         compatible = "mediatek,mt7623-xhci",
  832.                  "mediatek,mt8173-xhci";
  833.         reg = <0 0x1a1c0000 0 0x1000>,
  834.               <0 0x1a1c4700 0 0x0100>;
  835.         reg-names = "mac", "ippc";
  836.         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
  837.         clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
  838.              <&topckgen CLK_TOP_ETHIF_SEL>;
  839.         clock-names = "sys_ck", "free_ck";
  840.         power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
  841.         phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
  842.         status = "disabled";
  843.     };
  844.  
  845.     u3phy1: usb-phy@1a1c4000 {
  846.         compatible = "mediatek,mt7623-u3phy",
  847.                  "mediatek,mt2701-u3phy";
  848.         reg = <0 0x1a1c4000 0 0x0700>;
  849.         clocks = <&clk26m>;
  850.         clock-names = "u3phya_ref";
  851.         #address-cells = <2>;
  852.         #size-cells = <2>;
  853.         ranges;
  854.         status = "disabled";
  855.  
  856.         u2port0: usb-phy@1a1c4800 {
  857.             reg = <0 0x1a1c4800 0 0x0100>;
  858.             #phy-cells = <1>;
  859.             status = "okay";
  860.         };
  861.  
  862.         u3port0: usb-phy@1a1c4900 {
  863.             reg = <0 0x1a1c4900 0 0x0700>;
  864.             #phy-cells = <1>;
  865.             status = "okay";
  866.         };
  867.     };
  868.  
  869.     usb2: usb@1a240000 {
  870.         compatible = "mediatek,mt7623-xhci",
  871.                  "mediatek,mt8173-xhci";
  872.         reg = <0 0x1a240000 0 0x1000>,
  873.               <0 0x1a244700 0 0x0100>;
  874.         reg-names = "mac", "ippc";
  875.         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
  876.         clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
  877.              <&topckgen CLK_TOP_ETHIF_SEL>;
  878.         clock-names = "sys_ck", "free_ck";
  879.         power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
  880.         phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
  881.         status = "disabled";
  882.     };
  883.  
  884.     u3phy2: usb-phy@1a244000 {
  885.         compatible = "mediatek,mt7623-u3phy",
  886.                  "mediatek,mt2701-u3phy";
  887.         reg = <0 0x1a244000 0 0x0700>;
  888.         clocks = <&clk26m>;
  889.         clock-names = "u3phya_ref";
  890.         #address-cells = <2>;
  891.         #size-cells = <2>;
  892.         ranges;
  893.         status = "disabled";
  894.  
  895.         u2port1: usb-phy@1a244800 {
  896.             reg = <0 0x1a244800 0 0x0100>;
  897.             #phy-cells = <1>;
  898.             status = "okay";
  899.         };
  900.  
  901.         u3port1: usb-phy@1a244900 {
  902.             reg = <0 0x1a244900 0 0x0700>;
  903.             #phy-cells = <1>;
  904.             status = "okay";
  905.         };
  906.     };
  907.  
  908.     ethsys: syscon@1b000000 {
  909.         compatible = "mediatek,mt7623-ethsys",
  910.                  "mediatek,mt2701-ethsys",
  911.                  "syscon";
  912.         reg = <0 0x1b000000 0 0x1000>;
  913.         #clock-cells = <1>;
  914.         #reset-cells = <1>;
  915.     };
  916.  
  917.     eth: ethernet@1b100000 {
  918.         compatible = "mediatek,mt7623-eth",
  919.                  "mediatek,mt2701-eth",
  920.                  "syscon";
  921.         reg = <0 0x1b100000 0 0x20000>;
  922.         interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
  923.                  <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
  924.                  <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
  925.         clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
  926.              <&ethsys CLK_ETHSYS_ESW>,
  927.              <&ethsys CLK_ETHSYS_GP1>,
  928.              <&ethsys CLK_ETHSYS_GP2>,
  929.              <&apmixedsys CLK_APMIXED_TRGPLL>;
  930.         clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
  931.         resets = <&ethsys MT2701_ETHSYS_FE_RST>,
  932.              <&ethsys MT2701_ETHSYS_GMAC_RST>,
  933.              <&ethsys MT2701_ETHSYS_PPE_RST>;
  934.         reset-names = "fe", "gmac", "ppe";
  935.         power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
  936.         mediatek,ethsys = <&ethsys>;
  937.         mediatek,pctl = <&syscfg_pctl_a>;
  938.         #address-cells = <1>;
  939.         #size-cells = <0>;
  940.         status = "disabled";
  941.     };
  942.  
  943.     hnat: hnat@1b000000 {
  944.         compatible = "mediatek,mt7623-hnat";
  945.         reg = <0 0x1b100000 0 0x3000>;
  946.         mtketh-wan = "wan";
  947.         resets = <&ethsys 0>;
  948.         reset-names = "mtketh";
  949.     };
  950.  
  951.     crypto: crypto@1b240000 {
  952.         compatible = "mediatek,mt7623-crypto";
  953.         reg = <0 0x1b240000 0 0x20000>;
  954.         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
  955.                  <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
  956.                  <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
  957.                  <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
  958.                  <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
  959.         clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
  960.              <&ethsys CLK_ETHSYS_CRYPTO>;
  961.         clock-names = "ethif","cryp";
  962.         power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
  963.         status = "disabled";
  964.     };
  965.     bdpsys: syscon@1c000000 {
  966.         compatible = "mediatek,mt7623-bdpsys",
  967.                  "mediatek,mt2701-bdpsys",
  968.                  "syscon";
  969.         reg = <0 0x1c000000 0 0x1000>;
  970.         #clock-cells = <1>;
  971.         #reset-cells = <1>;
  972.     };
  973. };
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