Operazioni

-------------------------------------------------------------------------------
--
-- Title       : operazioni
-- Design      : compito
-- Author      : Mario
-- Company     : UNICT
--
-------------------------------------------------------------------------------
--
-- File        : d:\My_Designs\07_02_2017_es2_2\compito\src\operazioni.vhd
-- Generated   : Sat Nov 18 14:59:45 2017
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {operazioni} architecture {operazioni}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_signed.all;
use IEEE.STD_LOGIC_arith.all;

entity operazioni is
     port(
         start : in STD_LOGIC;
         clk : in STD_LOGIC;
         Din : in STD_LOGIC_VECTOR(31 downto 0);
         fine : out STD_LOGIC;
         Dout : out STD_LOGIC_VECTOR(31 downto 0)
         );
end operazioni;

--}} End of automatically maintained section

architecture operazioni of operazioni is

type stati is (idle, decode, exelw, exeand, exeadd, exeshl);
type reg is array(0 to 3) of STD_LOGIC_VECTOR(31 downto 0);
signal state: stati;
signal R: reg;
signal OP: STD_LOGIC_VECTOR(7 downto 0);
signal A: STD_LOGIC_VECTOR(31 downto 0);
signal cicli: INTEGER range 0 to 2;
signal enop, endecode, enexelw, enexeand, enexeadd, enexeshl: STD_LOGIC;

function nextstate(state: stati; start: STD_LOGIC; op: STD_LOGIC_VECTOR(1 downto 0); A: STD_LOGIC_VECTOR(31 downto 0); cicli: INTEGER range 0 to 2)
return stati
is
variable nxt: stati;
begin
    case state is
        when idle => if start = '1' then nxt := decode;
        else nxt := idle;
        end if;

        when decode =>
            case op is
                when "00" => nxt := exelw;
                when "01" => nxt := exeand;
                when "10" => nxt := exeadd;
                when "11" => nxt := exeshl;
                when others => null;
            end case;

        when exelw => nxt := idle;
        when exeand => nxt := idle;

        when exeadd => if cicli < 2 and conv_integer(A) /= 0 then nxt := exeadd;
        else nxt := idle;
        end if;

        when exeshl => if cicli < 1 then nxt := exeshl;
        else nxt := idle;
        end if;

    end case;
    return nxt;
end nextstate;

function aluoperation(op: STD_LOGIC_VECTOR(1 downto 0); R: reg; A: STD_LOGIC_VECTOR(31 downto 0); s1, s2: INTEGER range 0 to 3)
return STD_LOGIC_VECTOR
is
variable tmp: STD_LOGIC_VECTOR(31 downto 0);
begin
    case op is
        when "00" => tmp := A;
        when "01" => tmp := R(s1) and R(s2);
        when "10" => tmp := R(s1) + A;
        when "11" => tmp := shl(R(s1), R(s2));
        when others => null;
    end case;
    return tmp;
end aluoperation;

begin

    -- UNITA' DI CONTROLLO --

    process(clk)
    begin
        if clk'event and clk = '0' then
            state <= nextstate(state, start, OP(1 downto 0), A, cicli);
        end if;
    end process;

    -- ENABLE --

    enop <= '1' when state = idle and start = '1' else '0';
    endecode <= '1' when state = decode else '0';
    enexelw <= '1' when state = exelw else '0';
    enexeand <= '1' when state = exeand else '0';
    enexeadd <= '1' when state = exeadd else '0';
    enexeshl <= '1' when state = exeshl else '0';

    -- DATAPATH --

    process(clk)
    variable s1, s2, d: INTEGER range 0 to 3;
    begin
        if clk'event and clk = '0' then
            if enop = '1' then
                op <= din(7 downto 0);
                cicli <= 0;
            end if;

            if endecode = '1' then
                if op(0) = '0' then
                    A <= din;
                end if;
                d := conv_integer(unsigned(op(7 downto 6)));
                s1 := conv_integer(unsigned(op(5 downto 4)));
                s2 := conv_integer(unsigned(op(3 downto 2)));
            end if;

            if enexelw = '1' or enexeand = '1' then
                dout <= aluoperation(op(1 downto 0), R, A, s1, s2);
                r(d) <= aluoperation(op(1 downto 0), R, A, s1, s2);
            end if;

            if enexeadd = '1' then
                if cicli = 2 or conv_integer(A) = 0 then
                    dout <= aluoperation(op(1 downto 0), R, A, s1, s2);
                    r(d) <= aluoperation(op(1 downto 0), R, A, s1, s2);
                else
                    cicli <= cicli + 1;
                end if;
            end if;

            if enexeshl = '1' then
                if cicli = 1 then
                    dout <= aluoperation(op(1 downto 0), R, A, s1, s2);
                    r(d) <= aluoperation(op(1 downto 0), R, A, s1, s2);
                else
                    cicli <= cicli + 1;
                end if;
            end if;

            if enexelw = '1' or
                enexeand = '1' or
                (enexeadd = '1' and (cicli = 2 or conv_integer(A) = 0)) or
                (enexeshl = '1' and cicli = 1) then
                fine <= '1';
            else
                fine <= '0';
            end if;
        end if;
    end process;
end operazioni;