RAM ROM VHDL MAJA

----------------------------------------------------------------------------------
-- Company:
-- Engineer: Marko Rajinac E13624
--
-- Create Date:    13:34:01 12/12/2011
-- Design Name:
-- Module Name:    instr_rom - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity instr_rom is
    Port (
     iA : in STD_LOGIC_VECTOR (15 downto 0);
     oQ : out  STD_LOGIC_VECTOR (14 downto 0));
end instr_rom;

architecture Behavioral of instr_rom is
    type tMEMORY is array (0 to 31) of std_logic_vector(14 downto 0);
    signal sADRESS : integer RANGE 0 to 31;

    constant cMOV STD_LOGIC_VECTOR(3 downto 0) := "0000";
    constant cADD STD_LOGIC_VECTOR (3 downto 0) := "0001";
    constant cSUB STD_LOGIC_VECTOR(3 downto 0) := "0010";
    constant cSHIFT STD_LOGIC_VECTOR(3 downto 0) :="0011";

    constant cR0 STD_LOGIC_VECTOR(2 downto 0) := "000";
    constant cR1 STD_LOGIC_VECTOR(2 downto 0) := "001";
    constant cR2 STD_LOGIC_VECTOR(2 downto 0) := "010";
    constant cR3 STD_LOGIC_VECTOR(2 downto 0) := "011";

    constant cJMP STD_LOGIC_VECTOR(5 downto 0) := "1000001";


    constant cROM : tMEMORY :=(
        "00" & cADD & sR3 & cR1 & cR2,
        "100000011000000",--0-- ucitaj iz memorije u r3
        "000110010010000",--1-- uvecaj r2 za 1
        "000001000000010",--2-- saberi r0 i r2 i upisi u r0
        "001000000000000",--3-- siftuj r0 u levo
        "000110001001000",--4-- uvecaj r1 za 1
        "000010111010001",--5-- oduzmi r2 i r1 i stavi ih u r7
        "010101000000011",--6-- ako nije 0 skoci na 3
        cJMP & "000000000", -- jmp na  pocetak
        "000000001110000",--7-- prebaci r6 koji je x0000 u r1 kako bi ga postavio na 0
        "000111011011000",--8-- umanji r3 za 1
        "010101000000001",--9-- ako nije nula skoci na 1 - inace je kraj
        "000110110110000",--10-- uvecaj reg6 za jedan
        "110000000000110",--11-- smesti u drugu lokaciju u memoriji rezultat iz r0
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "000000000000000",
        "010000000011111" --beskonacna petlja - bezuslovni skok na sRam(31)
        );
begin

    sADRESS<=conv_integer(iA);
    oQ <= cROM(sADRESS);

end Behavioral;