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-- Company:
-- Engineer:
--
-- Create Date:    16:58:57 03/05/2019
-- Design Name:
-- Module Name:    wyswietlacz - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity wyswietlacz is
    Port ( sw_i : in  STD_LOGIC_VECTOR (7 downto 0);
           btn_i : in  STD_LOGIC_VECTOR (3 downto 0);
           led7_an_o : out  STD_LOGIC_VECTOR (3 downto 0);
           led7_seg_o : out  STD_LOGIC_VECTOR (7 downto 0);
           clk_i : in  STD_LOGIC);
end wyswietlacz;

architecture Behavioral of wyswietlacz is
    constant n : integer := 3;
    signal counter : integer range 0 to n - 1 := 0;
    signal clk_divided : std_logic := '0';
    type t_chars is array (15 downto 0) of std_logic_vector(7 downto 0);
    signal chars : t_chars;


begin
    q <= '0';
     chars(0)(7 downto 1) <= "0000001";
     chars(1)(7 downto 1) <= "1001111";
     chars(2)(7 downto 1) <= "0010010";
     chars(3)(7 downto 1) <= "0000110";
     chars(4)(7 downto 1) <= "1001100";
     chars(5)(7 downto 1) <= "0100100";
     chars(6)(7 downto 1) <= "0100000";
     chars(7)(7 downto 1) <= "0001111";
     chars(8)(7 downto 1) <= "0000000";
     chars(9)(7 downto 1) <= "0000100";
     chars(10)(7 downto 1) <= "0000010";
     chars(11)(7 downto 1) <= "1100000";
     chars(12)(7 downto 1) <= "0110001";
     chars(13)(7 downto 1) <= "1000010";
     chars(14)(7 downto 1) <= "0110000";
     chars(15)(7 downto 1) <= "0111000";
     chars(15 downto 0)(0) <= (others => q);
     p_clk_divider: process(clk_i)
        begin
            if (rising_edge(clk_i)) then
                counter <= counter + 1;
                if (counter = (n/2)) then
                    clk_divided <= '1';
                elsif (counter = n-1) then
                    clk_divided <= '0';
                    counter <= 0;
                end if;
            end if;
    end process;

end Behavioral;