library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Binary_to_7Seg is
    Port ( bin : in  STD_LOGIC_VECTOR (7 downto 0);
              sign : in std_logic;
              sign_7 : out  STD_LOGIC_VECTOR (6 downto 0);
              ones_7 : out  STD_LOGIC_VECTOR (6 downto 0);
           tens_7 : out  STD_LOGIC_VECTOR (6 downto 0);
           hundreds_7 : out  STD_LOGIC_VECTOR (6 downto 0));
end Binary_to_7Seg;

architecture Behavioral of Binary_to_7Seg is

function bcd_to_seg(Value: in std_logic_vector(0 to 3)) return std_logic_vector is
begin
   case Value is
            when "0000"=> return "1000000";  -- '0'
            when "0001"=> return "1111001";  -- '1'
            when "0010"=> return "0100100";  -- '2'
            when "0011"=> return "0110000";  -- '3'
            when "0100"=> return "0011001";  -- '4'
            when "0101"=> return "0010010";  -- '5'
            when "0110"=> return "0000010";  -- '6'
            when "0111"=> return "1111000";  -- '7'
            when "1000"=> return "0000000";  -- '8'
            when "1001"=> return "0010000";  -- '9'
            when others=> return "1111111";
    end case;
end bcd_to_seg;

begin
    process (bin)

    variable temp : STD_LOGIC_VECTOR (7 downto 0);
     variable ones : STD_LOGIC_VECTOR (3 downto 0);
     variable tens : STD_LOGIC_VECTOR (3 downto 0);
     variable hundreds : STD_LOGIC_VECTOR (3 downto 0);
     variable sign_7_temp : STD_LOGIC_VECTOR (6 downto 0);

    -- Variable to store the output BCD number organized as follows:
    --   hundreds = bcd(11 downto 8)
    --   tens = bcd(7 downto 4)
    --   units = bcd(3 downto 0)
    variable bcd : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');

    begin
        -- Zero the bcd variable.

        bcd := (others => '0');

        -- Read the input binary value into the temp variable.
        temp(7 downto 0) := bin;

          if bin(7) = '1' and sign = '1' then
                temp := (not temp) + 1;
                sign_7_temp := "0111111";
          end if;

          if bin(7) = '0' and sign = '1' then
                sign_7_temp := "0111001";
          end if;

          if bin(7) = '0' and sign = '0' then
                sign_7_temp := "1111111";
          end if;

        -- Cycle 8 times as we have 8 input bits.
        for i in 0 to 7 loop

            if bcd(3 downto 0) > 4 then
                bcd(3 downto 0) := bcd(3 downto 0) + 3;
            end if;

            if bcd(7 downto 4) > 4 then
                bcd(7 downto 4) := bcd(7 downto 4) + 3;
            end if;

            -- Hundreds can't be > 4 for an 8-bit input number
            -- so don't need to do anything to upper 4 bits of bcd.

            -- Shift bcd left by 1 bit, copy MSB of temp into LSB of bcd.
            bcd := bcd(10 downto 0) & temp(7);

            -- Shift temp left by 1 bit.
            temp := temp(6 downto 0) & '0';

        end loop;

        -- Extract outputs from bcd.
        ones := STD_LOGIC_VECTOR(bcd(3 downto 0));
        tens := STD_LOGIC_VECTOR(bcd(7 downto 4));
        hundreds := STD_LOGIC_VECTOR(bcd(11 downto 8));

          ones_7 <= bcd_to_seg(bcd(3 downto 0));
        tens_7 <= bcd_to_seg(bcd(7 downto 4));
        hundreds_7 <= bcd_to_seg(bcd(11 downto 8));

          sign_7 <= sign_7_temp;

          if tens = "0000" and hundreds = "0000" and sign = '1' then
                tens_7 <= sign_7_temp;
                hundreds_7 <= "1111111";
                sign_7 <= "1111111";
          end if;

          if tens /= "0000" and hundreds = "0000" and sign = '1' then
                hundreds_7 <= sign_7_temp;
                sign_7 <= "1111111";
          end if;

          if tens = "0000" and hundreds = "0000" and sign = '0' then
                hundreds_7 <= "1111111";
                tens_7 <= "1111111";
                sign_7 <= "1111111";
          end if;

          if tens /= "0000" and hundreds = "0000" and sign = '0' then
                hundreds_7 <= "1111111";
                sign_7 <= "1111111";
          end if;

    end process;

end Behavioral;