Dzielnik_test

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-- Company:
-- Engineer:
--
-- Create Date:   12:20:09 03/16/2019
-- Design Name:
-- Module Name:   C:/ZapiskiStudenckie/Dzielnik/Dzielnik_test.vhd
-- Project Name:  Dzielnik
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Dzielnik_kod
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY Dzielnik_test IS
END Dzielnik_test;

ARCHITECTURE behavior OF Dzielnik_test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Dzielnik_kod
    PORT(
         CLK : IN  std_logic;
         RST : IN  std_logic;
         LED : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal CLK : std_logic := '0';
   signal RST : std_logic := '0';

    --Outputs
   signal LED : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: Dzielnik_kod PORT MAP (
          CLK => CLK,
          RST => RST,
          LED => LED
        );

   -- Clock process definitions
   CLK_process :process
   begin
        CLK <= '0';
        wait for CLK_period/2;
        CLK <= '1';
        wait for CLK_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
        RST <= '1';
      -- hold reset state for 100 ns.
      wait for 100 ns;
        RST <= '0';
        wait for 300 ns;
        RST <= '1';
        wait for 5 ns;
        RST <= '0';
      -- insert stimulus here
      wait;
   end process;

END;