library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity calculator_core is port(
    inc, sel, rst : in std_logic;
    stageOut : out std_logic_vector(2 downto 0);
    outputVal : out std_logic_vector(7 downto 0));
end calculator_core;

architecture behavioral of calculator_core is
signal temp : std_logic_vector (7 downto 0);
signal mode : std_logic_vector (1 downto 0);
shared variable operand : std_logic_vector (7 downto 0);
signal operandtwo : std_logic_vector (7 downto 0);
signal incflag : std_logic_vector(1 downto 0);
begin
    process(sel,rst,incflag)    -- process the opcode selection (sel button -- S3)
    begin
        if(sel'event and sel = '0') then
            case mode(1 downto 0) is
                when "00" =>
                    stageOut <= "001";
                    mode <= "01";
                when "01" =>
                    stageOut <= "010";
                    mode <= "10";
                when "10" =>
                    stageOut <= "011";
                    mode <= "11";
                when "11" =>
                    stageOut <= "000";
                    mode <= "00";
            end case;
        end if;
        -- reset the calc if rst is pressed
        if(rst = '0') then
            stageOut(2 downto 0) <= "000";
            mode(1 downto 0) <= "00";
            temp(7 downto 0) <= "00000000";
            incflag(1 downto 0) <= "00";
            operandtwo(7 downto 0) <= "00000000";
        end if;
        if(inc'event and inc = '0') then
            operand := operand + 1;
            outputVal <= operand;
        end if;
    end process;
    -- outputVal <= temp;
end behavioral;