Clock_Setting_Correct

static void SystemClock_Config(void)
{
  RCC_ClkInitTypeDef RCC_ClkInitStruct;
  RCC_OscInitTypeDef RCC_OscInitStruct;

  /* Enable Power Control clock */
  //__HAL_RCC_PWR_CLK_ENABLE();
  RCC->APB1ENR |= 0x10000000;   // Enable PWREN bit (page - 183 of RM)


  /* The voltage scaling allows optimizing the power consumption when the device is
     clocked below the maximum system frequency, to update the voltage scaling value
     regarding system frequency refer to product datasheet.  */
  //__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
  PWR->CR |= 0x00004000;    //VOS bit = 01 (page - 145 or RM)

  // Page - 216 of RM
  RCC->CR |= 0x00010000;    // HSE ON
  while((RCC->CR & 0x00020000) == 0);   // Wait till HSE is ready

  // Page - 226 of RM
  RCC->PLLCFGR = 0;
  RCC->PLLCFGR |= 0x00400000;   // PLL source is HSE
  RCC->PLLCFGR |= 0x00000008;   // M = 8
  RCC->PLLCFGR |= 0x00000000 + ((uint32_t)336 << 6);    // N = 336
  RCC->PLLCFGR |= 0x00000000 + (((uint32_t)2 >> 1) - 1);    // P = 2
  RCC->PLLCFGR |= 0x00000000 + ((uint32_t)7 << 24); // Q = 7

  RCC->CR |= 0x01000000;    // PLL ON
  while((RCC->CR & 0x02000000) == 0);   // Wait till PLL is ready

  /* Enable HSI Oscillator and activate PLL with HSI as source */
//  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
//  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
//  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
//  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
//  RCC_OscInitStruct.PLL.PLLM = 8;
//  RCC_OscInitStruct.PLL.PLLN = 336;
//  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
//  RCC_OscInitStruct.PLL.PLLQ = 7;
//  HAL_RCC_OscConfig(&RCC_OscInitStruct);


//  RCC->CFGR |= 0x00000002; // SW = 0b10 = PLL used as system clock
//  while((RCC->CFGR & 0x00000008) == 0);   // Make sure SWS = 0b10 = PLL is really selected

  RCC->CFGR |= 0x00000000;  // HPRE = 0 = Div by 1 (no division), AHB = 168MHz
  RCC->CFGR |= 0x00000000 + ((uint32_t)5 << 10); // PPRE1 = 5, APB1 = div by 4 = 42MHz
  RCC->CFGR |= 0x00000000 + ((uint32_t)4 << 13); // PPRE2 = 4, APB2 = div by 2 = 84MHz
//  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, 2);
  uint32_t temp = RCC->CFGR;
  temp = temp | 0x00000002;
  RCC->CFGR = temp;
  FLASH->ACR |= 0x00000005; // FLASH_LATENCY_5


  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
//  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
//  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
//  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
//  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
//  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
//  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);

  idNumber = DBGMCU->IDCODE;
  idNumber = idNumber >> 16;

  if(idNumber == 0x1001)
  {
      FLASH->ACR |= 0x00000100; // Enable prefetch buffer
  }
//  /* STM32F405x/407x/415x/417x Revision Z devices: prefetch is supported  */
//  if (HAL_GetREVID() == 0x1001)
//  {
//    /* Enable the Flash prefetch */
//    __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
//  }
}