library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Ram is
    Port ( CLK : in STD_LOGIC;
           WE : in STD_LOGIC;
           ADDR_READ_X : in STD_LOGIC_VECTOR(10 downto 0);
           ADDR_WRITE : in STD_LOGIC_VECTOR(10 downto 0);
           DATA_IN : in STD_LOGIC_VECTOR(8 downto 0);
           DATA_OUT : out STD_LOGIC_VECTOR(8 downto 0)
         );
end Ram;

architecture behavioral of Ram is
    type ram_type is array (0 to 799) of STD_LOGIC_VECTOR(8 downto 0);
    signal ram : ram_type :=
     ( 0 to 99 => "000000000",
     100 to 199 => "000001111",
     200 to 299 => "000111111",
     300 to 399 => "010011111",
    400 to 499 => "100011111",
     500 to 599 => "111100000",
     600 to 699 => "111111000",
     700 to 799 => "111111111");

begin
    process(CLK)
     begin
        if(CLK'event and CLK = '1')then
            --if(WE = '1')then
             -- ram(conv_integer(ADDR_WRITE)) <= DATA_IN;
            --end if;
            if(ADDR_READ_X < 800)then
             DATA_OUT <= ram(conv_integer(ADDR_READ_X));
            end if;
        end if;
    end process;
end behavioral;