LIBRARY IEEE;
USE work.CLOCKS.all;   -- Entity that uses CLOCKS
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_textio.all;
USE std.textio.all;
USE work.txt_util.all;

ENTITY tb_JOSEPH_4_STAGE_ADDER IS
END;

ARCHITECTURE TESTBENCH OF tb_JOSEPH_4_STAGE_ADDER IS
    constant P:integer:= 16;
    constant W:integer:= 4;
    constant E:integer:= 8;

---------------------------------------------------------------
-- COMPONENTS
---------------------------------------------------------------

COMPONENT CLOCK
    port(CLK: out std_logic);
END COMPONENT;

COMPONENT JOSEPH_4_STAGE_ADDER          -- In/out Ports

generic(P: integer:=16;
    W: integer:=4;
    E: integer:=8
      );

port(CLK: in std_logic;
       Reset: in std_logic;
       EN: in std_logic;
       OP_A: in std_logic_vector(P-1 downto 0);
       OP_B: in std_logic_vector(P-1 downto 0);
       OP_Q: out std_logic_vector(P-1 downto 0);
       OP_F: out std_logic_vector(W-2 downto 0)
     );
END COMPONENT;

---------------------------------------------------------------
-- Read/Write FILES
---------------------------------------------------------------


FILE in_file : TEXT open read_mode is   "JOSEPH_FULL_ADDER_INPUT.txt";   -- Inputs, reset, enr,enl
FILE exo_file : TEXT open read_mode is  "JOSEPH_FULL_ADDER_OUTPUT.txt";   -- Expected output (binary)
FILE out_file : TEXT open  write_mode is  "AMOO_EVENPD_Book_dataout_dacus.txt";
FILE xout_file : TEXT open  write_mode is "AMOO_EVENPD_Book_TestOut_dacus.txt";
FILE hex_out_file : TEXT open  write_mode is "AMOO_EVENPD_Book_hex_out_dacus.txt";
---------------------------------------------------------------
-- SIGNALS
---------------------------------------------------------------

  SIGNAL CLK: STD_LOGIC;
  SIGNAL OP_A: STD_LOGIC_VECTOR(P-1 downto 0):= (OTHERS => 'X');
  SIGNAL Reset: STD_LOGIC;
  SIGNAL EN: STD_LOGIC;
  SIGNAL OP_B: STD_LOGIC_VECTOR(P-1 downto 0):= (OTHERS => 'X');
  SIGNAL OP_F: STD_LOGIC_VECTOR(W-2 downto 0):= (OTHERS => 'X');
  SIGNAL OP_Q : STD_LOGIC_VECTOR(P-1 downto 0):= (OTHERS => 'X');
  SIGNAL Exp_OP_Q : STD_LOGIC_VECTOR(P-1 downto 0):= (OTHERS => 'X');
  SIGNAL Exp_OP_F : STD_LOGIC_VECTOR(W-2 downto 0):= (OTHERS => 'X');
  SIGNAL Test_OP_Q : STD_LOGIC:='X';
  SIGNAL Test_OP_F : STD_LOGIC:='X';
  SIGNAL LineNumber: integer:=0;

---------------------------------------------------------------
-- BEGIN
---------------------------------------------------------------

BEGIN

---------------------------------------------------------------
-- Instantiate Components
---------------------------------------------------------------


U0: CLOCK port map (CLK );
InstJOSEPH_4_STAGE_ADDER : JOSEPH_4_STAGE_ADDER  generic map (P, W, E)
port map (CLK, Reset, EN, OP_A, OP_B, OP_Q, OP_F);

---------------------------------------------------------------
-- PROCESS
---------------------------------------------------------------
PROCESS

variable in_line, exo_line : LINE;
variable comment, xcomment : string(1 to 128);
variable i : integer range 1 to 128;
variable simcomplete : boolean;

variable vOP_A   : std_logic_vector(P-1 downto 0):= (OTHERS => 'X');
variable vOP_B   : std_logic_vector(P-1 downto 0):= (OTHERS => 'X');
variable vReset   : std_logic:= '0';
variable vEN: std_logic:= '0';
variable vOP_Q : std_logic_vector(P-1 downto 0):= (OTHERS => 'X');
variable vOP_F: std_logic_vector(W-2 downto 0):= (OTHERS => 'X');
variable vExp_OP_Q : std_logic_vector(P-1 downto 0):= (OTHERS => 'X');
variable vExp_OP_F : std_logic_vector(W-2 downto 0):= (OTHERS => 'X');
variable vTest_OP_Q : std_logic := '0';
variable vTest_OP_F : std_logic := '0';
variable vlinenumber: integer;

BEGIN

simcomplete := false;

while (not simcomplete) LOOP

    if (not endfile(in_file) ) then
        readline(in_file, in_line);
    else
        simcomplete := true;
    end if;

    if (not endfile(exo_file) ) then
        readline(exo_file, exo_line);
    else
        simcomplete := true;
    end if;

    if (in_line(1) = '-') then  --Skip comments
        next;
    elsif (in_line(1) = '.')  then  --exit Loop
      Test_OP_Q <= 'Z';
        simcomplete := true;
    elsif (in_line(1) = '#') then        --Echo comments to out.txt
      i := 1;
      while in_line(i) /= '.' LOOP
        comment(i) := in_line(i);
        i := i + 1;
      end LOOP;

    elsif (exo_line(1) = '-') then  --Skip comments
        next;
    elsif (exo_line(1) = '.')  then  --exit Loop
          Test_OP_Q  <= 'Z';
           simcomplete := true;
    elsif (exo_line(1) = '#') then        --Echo comments to out.txt
         i := 1;
       while exo_line(i) /= '.' LOOP
         xcomment(i) := exo_line(i);
         i := i + 1;
       end LOOP;


    ELSE      --Begin processing
                read(in_line, vOP_A);
        OP_A  <= vOP_A;

        read(in_line, vOP_B);
        OP_B  <= vOP_B;

        read(in_line, vReset);
        Reset  <= vReset;

        read(in_line, vEN);
        EN  <= vEN;




        read(exo_line, vexp_OP_Q );
        read(exo_line, vexp_OP_F);
        read(exo_line, vTest_OP_Q );
        read(exo_line, vTest_OP_F);

    vlinenumber :=LineNumber;


    CYCLE(1,CLK);

    Exp_OP_Q      <= vexp_OP_Q;
    Exp_OP_F      <= vexp_OP_F;

    if (Exp_OP_Q = OP_Q) then
      Test_OP_Q <= '0';
    else
      Test_OP_Q <= 'X';
    end if;

    if (Exp_OP_F = OP_F) then
      Test_OP_F <= '0';
    else
      Test_OP_F <= 'X';
    end if;

    END IF;
    LineNumber<= LineNumber+1;

    END LOOP;
    WAIT;

    END PROCESS;

END TESTBENCH;


CONFIGURATION cfg_tb_JOSEPH_4_STAGE_ADDER OF tb_JOSEPH_4_STAGE_ADDER IS
    FOR TESTBENCH
        FOR InstJOSEPH_4_STAGE_ADDER: JOSEPH_4_STAGE_ADDER
        END FOR;
    END FOR;
END;