-- Unite de controle processeur pipeline
-- Version à compléter
-- Auteur :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

-- unité entité qui differencie les types de ports
entity control_unit is
port (  Clk : in std_logic;
    inst : in std_logic_vector(31 downto 0);
    Src_PC : out std_logic;

    Src1, Src2, Dest : out std_logic_vector(3 downto 0);
    Banc_ecr : out std_logic;
    Banc_src : out std_logic_vector(1 downto 0);

    cmd_ual : out std_logic_vector(1 downto 0);
    imm     : out std_logic_vector(15 downto 0);
    Z,N : in std_logic;

    Src_Op_B, Src_adr_branch : out std_logic;

    rw, bus_val : out std_logic
);
end control_unit;

-- architecture : mode de fonctionnnement (comportement)
architecture beh of control_unit is

signal di_ri :  std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
...

begin

    -- registre RI
    ri : process(clk)
    begin
        if clk'event and clk='0' then
            di_ri <= inst;
        end if;
    end process;
    di_codeop <= di_ri(31 downto 28);
    di_Dst : std_logic_vector(19 downto 16);
    di_Src1 : std_logic_vector(27 downto 24);
    di_Src2 : std_logic_vector(23 downto 20);
    di_imm : std_logic_vector(27 downto 24);
    -- decodeur
    ---------------------
    -- a vous
    process (di_codeOp)
        begin
            case di_codeop is
            -- ADD
                when "0001" =>
                di_cmd_ual => '1';
                di_Src_Op_B  = '1';
                di_Imm = std_logic_vector(15 downto 0);
                di_Src1 = Src1((31 downto 28));

                -- SUB
                when "0010" is
                --      "0010"&"0000"&"0010"&"0100"&"0000000000000000", -- 10 SUB R0, R2, R4
                di_cmd_ual => '1';
                di_Src_Op_B  = '1';
                di_Imm = '0000000000000000';
                di_Src1 = '0000';
                di_Src2 = '0010';
                di_Dst : '0100';

                -- SW
                    --"0011"&"0010"&"0100"&"0000"&"0000000000010000", -- 20 SW R4, 10(R2)
                when "00011" =>
                di_cmd_ual => '0';
                di_Src_Op_B  = '0';
                di_Imm = '0000000000010000';
                di_Src1 = '0010';
                di_Src2 = '0100';
                di_Dst : '0100';
        end c
    ---------------------


    -- registres pipeline
    -------EX
    ex : process(clk)
    begin
        if clk'event and clk='0' then
            ex_Bus_Donnees_out <= di_Bus_Donnees_out;
            ex_Dst <= di_Dst;
            ex_Src_Adr_Branch <= di_Src_Adr_Branch
            ex_Bus_Donnees_in <= di_Bus_Donnees_in
            ex_Banc8src <= di_Banc_Src;
            Src_PC = '1';

        end if;
    end process;
    ------MEM
    ex : process(clk)
    begin
        if clk'event and clk='0' then
            Src_Op_B
            Src_PC = '1';
        end if;
    end process;
    ------ER
    ex : process(clk)
    begin
        if clk'event and clk='0' then
            Src_PC = '1';
        end if;
    end process;
    -- a vous
    ---------------------
    ex : process(clk)
    begin
        if clk'event and clk='0' then
            ex_CmdUal <= CmdUal;
            ex_Src_Pc <= di_Src_Pc;
            ex_Imm <= di_Imm;
        end if;
    end process;
    CmdUal <= ex_cmdUal; --

end beh;