[Verilog] 104 Cell-based 初賽競賽題目

`timescale 1ns/10ps
module LBP ( clk, reset, gray_addr, gray_req, gray_ready, gray_data, lbp_addr, lbp_valid, lbp_data, finish);
input         clk;          // 時脈訊號
input         reset;        // 重置訊號
input         gray_ready;   // 當為 HIGH 才可對 HOST 索取資料
input  [ 7:0] gray_data;    // 灰階圖像資料
output [13:0] gray_addr;    // 灰階圖像位址
output        gray_req;     // 當為 HIGH 表示向 HOST 索取資料
output [13:0] lbp_addr;     // 二值圖像位址
output [ 7:0] lbp_data;     // 二值圖像資料
output        lbp_valid;    // 完成運算後為 HIGH
output        finish;       // 完成整張圖像後為 HIGH

// define to register
reg [13:0] gray_addr = 128;
reg        gray_req  = 0;
reg [13:0] lbp_addr  = 128;
reg [ 7:0] lbp_data  = 0;
reg        lbp_valid = 0;
reg        finish    = 0;

integer width   = 0;        // 寬度計算器
integer i       = 0;        // 計數器
integer j       = 0;        // 計數器
reg [ 8:0] block[ 8:0];     // 3*3 區塊
reg [14:0] addr = 128;      // 目前記憶體位址
reg [ 7:0] lbp  = 0;        // 計算的 LBP 值
reg [ 7:0] pow  = 1;        // 計算的 LBP 2^x 值
//====================================================================
// if (addr % 128 == 0 || (addr + 1) % 128 ==0) { continue; }
always @(posedge clk, posedge reset) begin
    if (reset) begin
        gray_addr = 0;
        gray_req  = 0;
        lbp_addr  = 129;
        lbp_data  = 0;
        lbp_valid = 0;
        finish    = 0;

        i         = 0;
        addr      = 129;
        width     = 1;
        lbp       = 0;
        pow       = 0;
    end else begin
        lbp_valid = 0;
        gray_req = 1;

        if (width == 0) begin
            lbp_data = 0;
            lbp_addr = addr;
            lbp_valid = 1;
            addr = addr + 1;
            width = width + 1;
            i = 0;
        end else if (width == 127) begin
            lbp_data = 0;
            lbp_addr = addr;
            lbp_valid = 1;
            addr = addr + 1;
            width = 0;
            i = 0;
        end else begin
            if (i > 0 && i <= 9) begin
                block[i - 1] = gray_data;
            end

            if (i == 0) begin
                gray_addr = addr - 129;
            end else if (i == 1) begin
                gray_addr = addr - 128;
            end else if (i == 2) begin
                gray_addr = addr - 127;
            end else if (i == 3) begin
                gray_addr = addr - 1;
            end else if (i == 4) begin
                gray_addr = addr;
            end else if (i == 5) begin
                gray_addr = addr + 1;
            end else if (i == 6) begin
                gray_addr = addr + 127;
            end else if (i == 7) begin
                gray_addr = addr + 128;
            end else if (i == 8) begin
                gray_addr = addr + 129;
            end else if (i == 9) begin
                lbp = 0;
                pow = 1;
                for (j = 0; j < 9; j = j + 1) begin
                    if (j != 4 && block[j] >= block[4]) begin
                        lbp = lbp + pow;
                    end

                    if (j != 4) begin
                        pow = pow * 2;
                    end
                end
                lbp_data = lbp;
                lbp_addr = addr;
                lbp_valid = 1;

                addr = addr + 1;
                width = width + 1;

                i = 0;
                gray_addr = addr - 129;
            end

            if (i < 9) begin
                i = i + 1;
            end
        end

        if (addr > 16255) begin
            gray_req  = 0;
            finish = 1;
        end
    end
end
//====================================================================
endmodule