library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Dtrig is
   port
   (
      c : in std_logic; reset : in std_logic; d : in std_logic; set : in std_logic;
      q : out std_logic; nq : out std_logic
   );
end entity Dtrig;

architecture BEH of Dtrig is

begin
   process (c, reset, d, set) is
   begin
     if (reset='1') then
         q <= '0';
     nq <= '1';
     elsif (set='1') then
         q <= '1';
         nq <= '0';
     elsif falling_edge(c) then
            if (d ='1') then
             q <= '1';
         nq <= '0';
            elsif (d ='0') then
             q<= '0';
         nq <= '1';
            end if;
      end if;
   end process;
end architecture BEH;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_Dtrig is
end tb_Dtrig;

architecture test1 of tb_Dtrig is

  component Dtrig
   port
   (
      c : in std_logic; reset : in std_logic; d : in std_logic; set : in std_logic;
      q : out std_logic; nq : out std_logic
   );
  end component;
  signal in_c, in_reset, in_d, in_set, out_q, out_nq: std_logic;
begin
p1 : Dtrig port map(in_c, in_reset, in_d, in_set, out_q, out_nq);
p2 : process
     begin
       in_c <= '1';
       wait for 10 ns;
       in_c <= '0';
       wait for 10 ns;
     end process;
p3 : process
     begin
       in_d <= '1';
       wait for 40 ns;
       in_d <= '0';
       wait for 115 ns;
     end process;
p4 : process
     begin
       in_reset <= '0';
       wait for 185 ns;
       in_reset <= '1';
       wait for 20 ns;
     end process;
p5 : process
     begin
        in_set <= '1';
        wait for 30 ns;
        in_set <= '0';
        wait for 75 ns;
     end process;
end test1;