library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Dzielnik_1024 is
    Port ( clk : in  STD_LOGIC;
           wyj : out  STD_LOGIC);
end Dzielnik_1024;

architecture Behavioral of Dzielnik_1024 is
signal licznik: std_logic_vector ( 7 downto 0 ) := "00000000";
begin
process (clk)
    begin
        if clk = '1' and clk'event then
        licznik <= licznik+1;
    end if;
end process;
wyj <= licznik(7);

end Behavioral;