abdullahq1

--180041239
--abdullah
--q1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparator is
port (
      clock: in std_logic;

      -- clock for synchronization

      m,n: in std_logic_vector(7 downto 0);

      -- Two inputs

      IAB: in std_logic; -- Expansion input ( Active low)
      Output: out std_logic -- Output = 0 when m = n
 );
end comparator;
architecture Behavioral of comparator is
signal AB: std_logic_vector(7 downto 0); -- temporary variables
signal Result: std_logic;
begin

 mn(0) <= (not m(0)) xnor (not n(0));
        -- combinational circuit
 mn(1) <= (not m(1)) xnor (not n(1));
 mn(2) <= (not m(2)) xnor (not n(2));
 mn(3) <= (not m(3)) xnor (not n(3));
 mn(4) <= (not m(4)) xnor (not n(4));
 mn(5) <= (not m(5)) xnor (not n(5));
 mn(6) <= (not m(6)) xnor (not n(6));
 mn(7) <= (not m(7)) xnor (not n(7));

 process(clock)
 begin
 if(rising_edge(clock))then
   if(mn = x"FF" and Imn = '0') then
         -- check whether m = n and Imn =0 or not
            Result <= '0';
    else
     Result <= '1';
    end if;
 end if;
 end process;
 Output <= Result;
end Behavioral;