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abdullahq1

Jan 7th, 2021
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  1. --180041239
  2. --abdullah
  3. --q1
  4. library IEEE;
  5. use IEEE.STD_LOGIC_1164.ALL;
  6.  
  7. entity comparator is
  8. port (
  9.       clock: in std_logic;
  10.  
  11.       -- clock for synchronization
  12.  
  13.       m,n: in std_logic_vector(7 downto 0);
  14.  
  15.       -- Two inputs
  16.  
  17.       IAB: in std_logic; -- Expansion input ( Active low)
  18.       Output: out std_logic -- Output = 0 when m = n
  19.  );
  20. end comparator;
  21. architecture Behavioral of comparator is
  22. signal AB: std_logic_vector(7 downto 0); -- temporary variables
  23. signal Result: std_logic;
  24. begin
  25.  
  26.  mn(0) <= (not m(0)) xnor (not n(0));        
  27.         -- combinational circuit
  28.  mn(1) <= (not m(1)) xnor (not n(1));
  29.  mn(2) <= (not m(2)) xnor (not n(2));
  30.  mn(3) <= (not m(3)) xnor (not n(3));
  31.  mn(4) <= (not m(4)) xnor (not n(4));
  32.  mn(5) <= (not m(5)) xnor (not n(5));
  33.  mn(6) <= (not m(6)) xnor (not n(6));
  34.  mn(7) <= (not m(7)) xnor (not n(7));
  35.  
  36.  process(clock)
  37.  begin
  38.  if(rising_edge(clock))then
  39.    if(mn = x"FF" and Imn = '0') then        
  40.          -- check whether m = n and Imn =0 or not
  41.             Result <= '0';
  42.     else
  43.      Result <= '1';
  44.     end if;
  45.  end if;
  46.  end process;
  47.  Output <= Result;
  48. end Behavioral;
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