library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity RamCtrlUnit is
   port(clk         : in  std_logic;
        reset       : in  std_logic;
        start       : in  std_logic;
        busy        : out std_logic;
        done        : out std_logic;
          savedCount  : out std_logic_vector(1 downto 0));
end RamCtrlUnit;


architecture Behavioral of RamCtrlUnit is

   type TState is (ST_IDLE, ST_SAVE_1,
                   ST_SAVE_2, ST_SAVE_3);

   signal s_currentState, s_nextState : TState;
begin
    process(clk)
    begin
        if (rising_edge(clk)) then
         if (reset = '1') then
            s_currentState <= ST_IDLE;
         else
            s_currentState <= s_nextState;
         end if;
     end if;
   end process;

    process(s_currentState, start)
   begin
      s_nextState <= s_currentState;

      case s_currentState is
      when ST_IDLE =>
         if (start = '1') then
            s_nextState <= ST_SAVE_1;
         end if;

      when ST_SAVE_1 =>
         s_nextState <= ST_SAVE_2;

      when ST_SAVE_2 =>
         s_nextState <= ST_SAVE_3;

        when ST_SAVE_3 =>
         s_nextState <= ST_IDLE;
      end case;

   end process;

    process(s_currentState)
   begin
      busy      <= '0';
      done      <= '0';
      savedCount <= "00";

      case s_currentState is
      when ST_IDLE =>
         done      <= '1';

      when ST_SAVE_1 =>
         busy      <= '1';
         savedCount  <= "01";

      when ST_SAVE_2 =>
            busy      <= '1';
         savedCount  <= "10";

      when ST_SAVE_3 =>
            busy      <= '1';
         savedCount  <= "11";
      end case;
   end process;
end Behavioral;