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Appendix C

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Jan 18th, 2018
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VHDL 1.81 KB | None | 0 0
  1. -- Interconnects
  2.   -- A
  3.   level_1_in_0 <= in0;
  4.   level_1_in_1 <= in1;
  5.   level_1_in_2 <= in2;
  6.   level_1_in_3 <= in3;
  7.   level_1_in_4 <= in4;
  8.   level_1_in_5 <= in5;
  9.   level_1_in_6 <= in6;
  10.   level_1_in_7 <= in7;
  11.   level_1_in_8 <= in8;
  12.   level_1_in_9 <= in9;
  13.   level_1_in_10 <= in10;
  14.   level_1_in_11 <= in11;
  15.   level_1_in_12 <= in12;
  16.   level_1_in_13 <= in13;
  17.   level_1_in_14 <= in14;
  18.   level_1_in_15 <= in15;
  19.  
  20.     -- B  
  21.   level_2_in_0 <= level_1_out_0;
  22.   level_2_in_1 <= level_1_out_1;
  23.   level_2_in_2 <= level_1_out_2;
  24.   level_2_in_3 <= level_1_out_3;
  25.   level_2_in_4 <= level_1_out_4;
  26.   level_2_in_5 <= level_1_out_5;
  27.   level_2_in_6 <= level_1_out_6;
  28.   level_2_in_7 <= level_1_out_7;
  29.   level_2_in_8 <= level_1_out_8;
  30.   level_2_in_9 <= level_1_out_9;
  31.   level_2_in_10 <= level_1_out_10;
  32.    
  33.     -- C
  34.       PROCESS(clk) BEGIN
  35.    if rising_edge(clk) then level_3_in_0 <= level_2_out_0;
  36.     level_3_in_1 <= level_2_out_1; level_3_in_2 <= level_2_out_2;
  37.     level_3_in_3 <= level_2_out_3; level_3_in_4 <= level_2_out_4;
  38.     level_3_in_5 <= level_2_out_5; level_3_in_6 <= level_2_out_6;
  39.     level_3_in_7 <= level_2_out_7;
  40.    end if;
  41.     end PROCESS;
  42.    
  43.     -- D
  44.     level_4_in_0 <= level_3_out_0;
  45.     level_4_in_1 <= level_3_out_1;
  46.     level_4_in_2 <= level_3_out_2;
  47.     level_4_in_3 <= level_3_out_3;
  48.     level_4_in_4 <= level_3_out_4;
  49.     level_4_in_5 <= level_3_out_5;
  50.    
  51.     -- E
  52.     PROCESS(clk) BEGIN
  53.     if rising_edge(clk) then level_5_in_0 <= level_4_out_0;
  54.      level_5_in_1 <= level_4_out_1; level_5_in_2 <= level_4_out_2;
  55.     level_5_in_3 <= level_4_out_3;
  56.     end if;
  57.     end PROCESS;
  58.    
  59.     -- F
  60.   level_6_in_0 <= level_5_out_0;
  61.   level_6_in_1 <= level_5_out_1;
  62.   level_6_in_2 <= level_5_out_2;
  63.      
  64.   outs <= outs_tmp;
  65.   outc <= outc_tmp;
  66.        
  67. END csa_tree_behav;
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