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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. entity CNT20_PLIS is port (  
  6.         CLK     : in std_logic;     --Sinchro signalas
  7.         RST     : in std_logic;     -- Reset signalas
  8.         CNT_CMD : in std_logic;     -- Komanda 
  9.         CNT_C   : out std_logic;    --Pernasa  
  10.         CNT_O   : out std_logic_vector(4 downto  0)
  11.         );
  12. end CNT20_PLIS;
  13.  
  14. architecture rtl of CNT20_PLIS is
  15.     signal CNT_A: unsigned (4 downto  0);
  16. begin  
  17.     process(CLK, RST, CNT_CMD)
  18.     begin
  19.         if RST = '0' then
  20.             CNT_A <= "00000";
  21.             CNT_C <= '1';      
  22.         elsif CLK'event and CLK = '1' and CNT_CMD = '1' then
  23.             if CNT_A < 19  then
  24.                 CNT_A <= CNT_A + 1;
  25.                 if CNT_A = 18 then
  26.                     CNT_C <= '0';  
  27.                 else
  28.                     CNT_C <= '1';
  29.                 end if;
  30.             else     
  31.                 CNT_C <= '1';
  32.                 CNT_A <= "00000";
  33.             end if;
  34.         end if;    
  35.     end process;
  36. CNT_O <= not(std_logic_vector(CNT_A)); 
  37. end rtl;
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