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-- Company:
-- Engineer:
--
-- Create Date:    18:37:34 12/07/2011
-- Design Name:
-- Module Name:    led01 - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity led01 is
    port (  --2. ZADATAK
            clk : in std_logic; -- signal takta
            reset : in std_logic; -- signal reseta
            ld7 : out std_logic; -- signal za upravljanje LED LD7

            --3. ZADATAK
            ra : in std_logic;
            rb : in std_logic;
            ld6 : out std_logic
            );
end led01;

architecture RTL of led01 is

    --2. ZADATAK
    signal brojilo: std_logic_vector(25 downto 0);

    --3. ZADATAK
    signal brojilo2: std_logic_vector(25 downto 0);
    signal korak: std_logic_vector(7 downto 0);
    signal dogadjaj: std_logic;
    signal smjer: std_logic;

    component encoder01
    port (
            clk               : in std_logic;
         reset             : in std_logic;

         rot_a             : in std_logic;
         rot_b             : in std_logic;

         rotary_event      : out std_logic;
         rotary_direction  : out std_logic
            );
    end component;

begin

    --3. ZADATAK
    enc: component encoder01 port map (clk => clk,
                                                reset => reset,
                                                rot_a => ra,
                                                rot_b => rb,
                                                rotary_event => dogadjaj,
                                                rotary_direction => smjer);

    --2. ZADATAK
    process (clk) is
    begin
        if rising_edge(clk) then
            if reset='1' then
                brojilo<=(others => '0');
            else
                brojilo<=brojilo+1;
            end if;
        end if;
    end process;

    ld7<=brojilo(25);

    --3. ZADATAK
    process (clk) is
    begin
        if rising_edge(clk) then
            if reset='1' then
                brojilo2<=(others => '0');
            else
                brojilo2<=brojilo2+korak;
            end if;
        end if;
    end process;

    process (clk) is
    begin
        if rising_edge(clk) then
            if reset='1' then
                korak<="00000001";
            else
                if dogadjaj='1' then
                    if smjer='1' and korak(7)/='1' then
                        korak<=korak(6 downto 0) & '0';
                    elsif smjer='0' and korak(0)/='1' then
                        korak<='0' & korak(7 downto 1);
                    end if;
                end if;
            end if;
        end if;
    end process;

    ld6<=brojilo2(25);

end RTL;