library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter8b is
port ( RESET,CLK,LD,UP : in std_logic;
 DIN : in std_logic_vector (7 downto 0);
 COUNT : out std_logic_vector (7 downto 0));
end counter8b;

architecture Behavioral of counter8b is

 signal t_cnt : std_logic_vector(7 downto 0);
begin
 process (CLK, RESET)
 begin
 if (RESET = '1') then
 t_cnt <= (others => '0'); -- clear
 elsif (rising_edge(CLK)) then
 if (LD = '1') then t_cnt <= DIN; -- load
 else
 if (UP = '1') then t_cnt <= std_logic_vector(unsigned(t_cnt) + 1); -- incr
 else t_cnt <= std_logic_vector(unsigned(t_cnt) - 1); -- decr
 end if;
 end if;
 end if;
 end process;
 COUNT <= t_cnt;


end Behavioral;