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- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.all;
- USE IEEE.NUMERIC_STD.all;
- USE IEEE.STD_LOGIC_SIGNED.all;
- ENTITY Lab6 IS
- PORT ( in_num : in STD_LOGIC_VECTOR(7 downto 0); --8-bit input
- HEX0,HEX1,HEX2,HEX3 : out STD_LOGIC_VECTOR(6 downto 0));
- End ENTITY Lab6;
- ARCHITECTURE behavior OF Lab6 IS
- SIGNAL Hundreds_Digit, Tens_Digit, Ones_Digit : STD_LOGIC_VECTOR(7 DOWNTO 0);
- SIGNAL Abs_num : STD_LOGIC_VECTOR(7 DOWNTO 0);
- CONSTANT BLANK : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1111111";
- CONSTANT ZERO : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000000";--g, f, e, d, c, b, a
- CONSTANT ONE : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1111001";
- CONSTANT TWO : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0100100";
- CONSTANT THREE : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0110000";
- CONSTANT FOUR : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011001";
- CONSTANT FIVE : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0010010";
- CONSTANT SIX : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000010";
- CONSTANT SEVEN : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1111000";
- CONSTANT EIGHT : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
- CONSTANT NINE : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000";
- CONSTANT a : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0001000";
- CONSTANT b : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000011";
- CONSTANT C : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000110";
- CONSTANT d : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0100001";
- CONSTANT E : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000110";
- CONSTANT F : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0001110";
- CONSTANT DASH : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0111111";
- BEGIN
- P1: PROCESS(in_num)
- BEGIN
- IF (in_num(7) = '1') THEN
- HEX3 <= DASH;
- ELSE
- HEX3 <= BLANK;
- END IF;
- END PROCESS;
- ----------------------------------------------------------------------------------------------------
- P2: PROCESS(in_num, Abs_num)
- BEGIN
- IF(in_num(7) = '0') THEN
- Abs_num <= in_num;
- ELSE
- Abs_num <= (NOT(in_num)) + 1;
- END IF;
- END PROCESS;
- ------------------------------------------------------------------------------------------------------
- Hundreds_Digit <= STD_LOGIC_VECTOR(UNSIGNED(Abs_num)/100);
- Tens_Digit <= STD_LOGIC_VECTOR(UNSIGNED(Abs_num)/10);
- Ones_Digit <= STD_LOGIC_VECTOR(UNSIGNED(Abs_num)REM 10);
- ------------------------------------------------------------------------------------------------------
- P3: PROCESS(Hundreds_Digit)
- BEGIN
- CASE Hundreds_Digit IS
- WHEN "00000001" => HEX2 <= ONE;
- WHEN "00000010" => HEX2 <= TWO;
- WHEN "00000011" => HEX2 <= THREE;
- WHEN "00000100" => HEX2 <= FOUR;
- WHEN "00000101" => HEX2 <= FIVE;
- WHEN "00000110" => HEX2 <= SIX;
- WHEN "00000111" => HEX2 <= SEVEN;
- WHEN "00001000" => HEX2 <= EIGHT;
- WHEN "00001001" => HEX2 <= NINE;
- WHEN OTHERS => HEX2 <= ZERO;
- END CASE;
- END PROCESS;
- ----------------------------------------------------------------------------------------------------------
- P4: PROCESS(Tens_Digit)
- BEGIN
- CASE Tens_Digit IS
- WHEN "00000001" => HEX1 <= ONE;
- WHEN "00000010" => HEX1 <= TWO;
- WHEN "00000011" => HEX1 <= THREE;
- WHEN "00000100" => HEX1 <= FOUR;
- WHEN "00000101" => HEX1 <= FIVE;
- WHEN "00000110" => HEX1 <= SIX;
- WHEN "00000111" => HEX1 <= SEVEN;
- WHEN "00001000" => HEX1 <= EIGHT;
- WHEN "00001001" => HEX1 <= NINE;
- WHEN OTHERS => HEX1 <= ZERO;
- END CASE;
- END PROCESS;
- ----------------------------------------------------------------------------------------------------------
- P5: PROCESS(Ones_Digit)
- BEGIN
- CASE Ones_Digit IS
- WHEN "00000001" => HEX0 <= ONE;
- WHEN "00000010" => HEX0 <= TWO;
- WHEN "00000011" => HEX0 <= THREE;
- WHEN "00000100" => HEX0 <= FOUR;
- WHEN "00000101" => HEX0 <= FIVE;
- WHEN "00000110" => HEX0 <= SIX;
- WHEN "00000111" => HEX0 <= SEVEN;
- WHEN "00001000" => HEX0 <= EIGHT;
- WHEN "00001001" => HEX0 <= NINE;
- WHEN OTHERS => HEX0 <= ZERO;
- END CASE;
- END PROCESS;
- END ARCHITECTURE behavior;
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