lab4sumatorvhdl

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-- Company:
-- Engineer:
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-- Create Date: 03/23/2018 02:35:36 PM
-- Design Name:
-- Module Name: sum8b - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sum8b is
 Port (
        x: in std_logic_vector(7 downto 0);
        y:in std_logic_vector(7 downto 0);
        tin: in std_logic;
        tout : out std_logic;
        sum: out std_logic_vector(7 downto 0)  );
end sum8b;

architecture Behavioral of sum8b is
signal G01,G23,G45,G67: std_logic;
signal P01,P23,P45,P67: std_logic;
signal S0, S1, S2, S3: STD_LOGIC_VECTOR(1 downto 0);
signal T0,T2,T4,T6,T8:std_logic;
begin
sum_S0: entity WORK.sum2b port map(
                x => x(1 downto 0),
                y => y(1 downto 0),
                tin => tin,
                sum=> S0,
                P => P01,
                G => G01);

sum_S1: entity WORK.sum2b port map(
                x => x(3 downto 2),
                y => y(3 downto 2),
                tin => T2,
                sum=> S1,
                P => P23,
                G => G23);

sum_S2: entity WORK.sum2b port map(
                x => x(5 downto 4),
                y => y(5 downto 4),
                tin => T4,
                sum=> S2,
                P => P45,
                G => G45);

sum_S3: entity WORK.sum2b port map(
               x => x(7 downto 6),
               y => y(7 downto 6),
               tin => T6,
               sum=> S3,
               P => P67,
               G => G67);

T2 <= G01 or (P01 and tin);
T4 <= G23 or ( P23 and T2  );
T6 <= G45 or ( P45 and T4  );
T8 <= G67 or ( P67 and T6  );

sum<=S3 & S2 & S1 & S0;

Tout <= T8;

end Behavioral;