library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity FSM_tb is
end;

architecture bench of FSM_tb is

  component FSM
  port (CLK : in std_logic;
   RSTn : in std_logic;
   CoinIn : in std_logic_vector (1 downto 0);
   Soda : out std_logic;
   CoinOut : out std_logic_vector (1 downto 0)
   );
  end component;

  signal CLK: std_logic;
  signal RSTn: std_logic;
  signal CoinIn: std_logic_vector (1 downto 0);
  signal Soda: std_logic;
  signal CoinOut: std_logic_vector (1 downto 0) ;

  constant clock_period: time := 10 ns;
  signal stop_the_clock: boolean;

begin

  uut: FSM port map ( CLK     => CLK,
                      RSTn    => RSTn,
                      CoinIn  => CoinIn,
                      Soda    => Soda,
                      CoinOut => CoinOut );

  stimulus: process
  begin

    -- Put initialisation code here




    -- Put test bench stimulus code here

    stop_the_clock <= true;
    wait;
  end process;

  clocking: process
  begin
    while not stop_the_clock loop
      clk <= '0', '1' after clock_period / 2;
      wait for clock_period;
    end loop;
    wait;
  end process;

end;